VLSI architectures for video compression-a survey

The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special, subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 /spl mu/m CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency. >

[1]  N. Ahmed,et al.  Discrete Cosine Transform , 1996 .

[2]  J. Limb,et al.  Measuring the Speed of Moving Objects from Television Signals , 1975, IEEE Trans. Commun..

[3]  Ciro Cafforio,et al.  Methods for measuring small displacements of television images , 1976, IEEE Trans. Inf. Theory.

[4]  J. D. Robbins,et al.  Motion-compensated television coding: Part I , 1979, The Bell System Technical Journal.

[5]  Anil K. Jain,et al.  Displacement Measurement and Its Application in Interframe Image Coding , 1981, IEEE Trans. Commun..

[6]  T Koga,et al.  MOTION COMPENSATED INTER-FRAME CODING FOR VIDEO CONFERENCING , 1981 .

[7]  F. Rocca,et al.  The Differential Method for Image Motion Estimation , 1983 .

[8]  R. Srinivasan,et al.  Predictive Coding Based on Efficient Motion Estimation , 1985, IEEE Trans. Commun..

[9]  B. Lee.  A new algorithm to compute the discrete cosine Transform , 1984 .

[10]  K. R. Rao,et al.  Motion Compensated Interframe Image Prediction , 1985, IEEE Trans. Commun..

[11]  P. Pirsch,et al.  Advances in picture coding , 1985, Proceedings of the IEEE.

[12]  Ming-Ting Sun,et al.  A family of vlsi designs for the motion compensation block-matching algorithm , 1989 .

[13]  Jan Biemond,et al.  A Pel-Recursive Wiener-Based Displacement Estimation Algorithm For Interframe Image Coding Applications , 1987, Other Conferences.

[14]  Hsueh-Ming Hang,et al.  An efficient block-matching algorithm for motion-compensated coding , 1987, ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[15]  Francis Jutand,et al.  A one chip VLSI for real time two-dimensional discrete cosine transform , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[16]  C. C. Stearns,et al.  A reconfigurable 64-tap transversal filter , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[17]  Richard L. Baker,et al.  Bit-Serial Architecture For Real Time Motion Compensation , 1988, Other Conferences.

[18]  Yukio Endo,et al.  Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP , 1989, J. VLSI Signal Process..

[19]  P.J. Hynes,et al.  A programmable 1400 MOPS video signal processor , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[20]  J.C. Carlach,et al.  TCAD: a 27 MHz 8*8 discrete cosine transform chip , 1989, International Conference on Acoustics, Speech, and Signal Processing,.

[21]  Jörn Ostermann,et al.  Object-oriented analysis-synthesis coding of moving images , 1989, Signal Process. Image Commun..

[22]  Peter Pirsch,et al.  Array architectures for block matching algorithms , 1989 .

[23]  Ting Chen,et al.  VLSI implementation of a 16*16 discrete cosine transform , 1989 .

[24]  T. Fukushima.  A survey of image processing LSIs in Japan , 1990, [1990] Proceedings. 10th International Conference on Pattern Recognition.

[25]  Monson H. Hayes,et al.  Improved pel-recursive motion estimation algorithms , 1990, IEEE Proceedings on Southeastcon.

[26]  Kou-Hu Tzou,et al.  High-Speed Programmable Ics For Decoding Of Variable-Length Codes , 1990, Optics & Photonics.

[27]  Masahiko Yoshimoto,et al.  A 24-b 50-ns digital image signal processor , 1990 .

[28]  M. GHANBARI,et al.  The cross-search algorithm for motion estimation [image coding] , 1990, IEEE Trans. Commun..

[29]  Luc De Vos,et al.  VLSI architectures for the hierarchical block-matching algorithm for HDTV applications , 1990, VCIP.

[30]  U. Totzek,et al.  CMOS VLSI implementation of the 2D-DCT with linear processor arrays , 1990, International Conference on Acoustics, Speech, and Signal Processing.

[31]  Sehat Sutardja,et al.  A 50 MHz vision processor , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[32]  F. Jutand,et al.  A high-speed low-cost DCT architecture for HDTV applications , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

[33]  K. K. Chau,et al.  VLSI implementation of a 2-D DCT in a compiler , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

[34]  Gregory K. Wallace,et al.  The JPEG still picture compression standard , 1991, CACM.

[35]  Toshihiro Minami,et al.  A 300-MOPS Video Signal Processor With A Parallel Architecture , 1991 .

[36]  T. Enomoto,et al.  250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI , 1991 .

[37]  A. Artieri,et al.  A dedicated circuit for real time motion estimation , 1991, Euro ASIC '91.

[38]  Hironori Yamauchi,et al.  Architecture and implementation of a highly parallel single-chip video DSP , 1992, IEEE Trans. Circuits Syst. Video Technol..

[39]  P. C. Jain,et al.  VLSI implementation of two-dimensional DCT processor in real time for video codec , 1992 .

[40]  Ming-Ting Sun,et al.  An all-ASIC implementation of a low bit-rate video codec , 1992, IEEE Trans. Circuits Syst. Video Technol..

[41]  Weiping Li,et al.  DCT/IDCT processor design for high data rate image coding , 1992, IEEE Trans. Circuits Syst. Video Technol..

[42]  D. Mlynek,et al.  A multiprocessors architecture for a HDTV motion estimation system , 1992 .

[43]  Peter A. Ruetz,et al.  A high-performance full-motion video compression chip set , 1992, IEEE Trans. Circuits Syst. Video Technol..

[44]  Shih-Fu Chang,et al.  Designing high-throughput VLC decoder. I. Concurrent VLSI architectures , 1992, IEEE Trans. Circuits Syst. Video Technol..

[45]  Stephen Purcell,et al.  C-Cube MPEG video processor , 1992, Electronic Imaging.

[46]  T.G. Noll,et al.  Pushing the performance limits due to power dissipation of future ULSI chips , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[47]  David G. Messerschmitt,et al.  Designing a high-throughput VLC decoder. I. Parallel decoding methods , 1992, IEEE Trans. Circuits Syst. Video Technol..

[48]  Takao Nishitani,et al.  An encoder/decoder chip set for the MPEG video standard , 1992, [Proceedings] ICASSP-92: 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[49]  Eric Petajan,et al.  Processing Hardware for Real-Time Video Coding , 1992 .

[50]  Konstantinos Konstantinides,et al.  Monolithic architectures for image processing and compression , 1992, IEEE Computer Graphics and Applications.

[51]  Makoto Suzuki,et al.  A 1000 MIPS BiCMOS microprocessor with superscalar architecture , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[52]  Chaur-Heh Hsieh,et al.  VLSI architecture for block-matching motion estimation algorithm , 1992, IEEE Trans. Circuits Syst. Video Technol..

[53]  S. P. Kim,et al.  Highly modular and concurrent 2-D DCT chip , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[54]  Douglas Bailey,et al.  Programmable vision processor/controller for flexible implementation of current and future image compression standards , 1992, IEEE Micro.

[55]  Peter A. Ruetz,et al.  A 160 Mpixel/s IDCT processor for HDTV , 1992, IEEE Micro.

[56]  Hisashi Kodama,et al.  A video digital signal processor with a vector-pipeline architecture , 1992 .

[57]  Gilles Privat,et al.  Guest Editor's Introduction: Processing Hardware for Real-Time Video Coding , 1992 .

[58]  Alice C. Parker,et al.  Predicting system-level area and delay for pipelined and nonpipelined designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[59]  Peter Pirsch,et al.  Multiprocessor performance for real-time processing of video coding applications , 1992, IEEE Trans. Circuits Syst. Video Technol..

[60]  T. Enomoto,et al.  A 300-MHz 16-b BiCMOS video signal processor , 1993 .

[61]  G.A. Uvieghara,et al.  A real time P*64/MPEG video encoder chip , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[62]  H. Mizutani,et al.  A motion video compression LSI with distributed arithmetic architecture , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[63]  Masahiko Yoshimoto,et al.  A half-pel precision motion estimation processor for NTSC-resolution video , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[64]  Peter Pirsch,et al.  A hierarchical multiprocessor architecture for video coding applications , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[65]  Osamu Kawai,et al.  Development of a VLSI chip set for H.261/MPEG-1 video codec , 1993, Other Conferences.

[66]  B. Ackland,et al.  The role of VLSI in multimedia , 1993, Symposium 1993 on VLSI Circuits.

[67]  Kou-Hu Tzou,et al.  1 - Video Coding Techniques: An Overview , 1993 .

[68]  Jhing-Fa Wang,et al.  A high throughput-rate architecture for 8*8 2D DCT , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[69]  Christopher J. Terman,et al.  A video decoder for H.261 video teleconferencing and MPEG stored interactive video applications , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[70]  Peter Pirsch,et al.  A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications , 1993, J. VLSI Signal Process..

[71]  S. Purcell,et al.  A single chip multistandard video codec , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[72]  Kenji Maeguchi,et al.  A single-chip MPEG2 video decoder LSI , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[73]  Hiroshi Takeno,et al.  Video DSP architecture for MPEG2 codec , 1994, Proceedings of ICASSP '94. IEEE International Conference on Acoustics, Speech and Signal Processing.

[74]  Moonkey Lee,et al.  A fast array architecture for block matching algorithm , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[75]  Lee-Sup Kim,et al.  200 MHz video compression macrocells using low-swing differential logic , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[76]  Chaitali Chakrabarti,et al.  VLSI architectures for hierarchical block matching , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[77]  Peter Gerken,et al.  Object-based analysis-synthesis coding of image sequences at very low bit rates , 1994, IEEE Trans. Circuits Syst. Video Technol..

[78]  Bryan D. Ackland.  The role of VLSI in multimedia , 1994 .

[79]  Liang-Gee Chen,et al.  Parallel architectures of 3-step search block-matching algorithm for video coding , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[80]  W. Gehrke,et al.  A hierarchical multiprocessor architecture based on heterogeneous processors for video coding applications , 1994, Proceedings of ICASSP '94. IEEE International Conference on Acoustics, Speech and Signal Processing.

[81]  Chris Toumazou,et al.  VLSI Implementation of MPEG Decoders , 1996 .