Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults

We propose a fault tolerance method for torus NoCs capable of increase the yield with minimal performance overhead. The proposed approach consists in detecting and diagnosing interconnect faults using BIST structures and activating alternative paths for the faulty links. Experimental results show that alternative fault-free paths are found by the dynamic routing for 95% of the diagnosed faults (stuck-at and pairwise shorts within a single link or between any two links).

[1]  R. Ubar,et al.  An External Test Approach for Network-on-a-Chip Switches , 2006, 2006 15th Asian Test Symposium.

[2]  Jin HoAhn,et al.  Test Scheduling of NoC-Based SoCs Using Multiple Test Clocks , 2006 .

[3]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[4]  Spyros Tragoudas,et al.  Interconnect testing for networks on chips , 2006, 24th IEEE VLSI Test Symposium.

[5]  Kees G. W. Goossens,et al.  Bringing communication networks on a chip: test and verification implications , 2003, IEEE Commun. Mag..

[6]  Altamiro Amadeu Susin,et al.  SoCIN: a parametric and scalable network-on-chip , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[7]  Alexandre M. Amory,et al.  A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip , 2008, IEEE Transactions on Computers.

[8]  Marcelo Lubaszewski,et al.  Diagnosis of interconnect shorts in mesh NoCs , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[9]  Partha Pratim Pande,et al.  On-line fault detection and location for NoC interconnects , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[10]  Partha Pratim Pande,et al.  BIST for network-on-chip interconnect infrastructures , 2006, 24th IEEE VLSI Test Symposium.