Dielectric breakdown in high-K metal gate: Measurement, device level model and application to circuit

Gate oxide breakdown is an important reliability issue. This mechanism is widely investigated at device level but the development of a compact model and the assessment at circuit level is much more complex to handle. We first characterize soft and hard breakdown with highlighting the different electrical signatures and sign change of the ratio source drain current. Then a transistor-level model of breakdown is presented. The model is calibrated for a large range of breakdown severity. Finally the model is used at circuit level. The impact of breakdown on both static current and frequency of ring oscillator is discussed.

[1]  R. T. Cakici,et al.  Device Characteristics and Equivalent Circuits for NMOS Gate-to-Drain Soft and Hard Breakdown in Polysilicon/SiON Gate Stacks , 2011, IEEE Transactions on Electron Devices.

[2]  J. Stathis.  Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits , 2001 .

[3]  J. Stathis,et al.  A model for gate-oxide breakdown in CMOS inverters , 2003, IEEE Electron Device Letters.

[4]  P. Cochat,et al.  Et al , 2008, Archives de pediatrie : organe officiel de la Societe francaise de pediatrie.

[5]  Sachin S. Sapatnekar,et al.  Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.