Performance Analysis and Implementation of Array Multiplier using various Full Adder Designs for DSP Applications: A VLSI Based Approach

Multipliers are the significant arithmetic units which are used in various VLSI and DSP applications. Besides their crucial necessity, Multipliers are also a main source for power dissipation. Hence prior importance must be given to lessen power dissipation in order to satisfy the overall power budget for various digital circuits and systems. Multiplier performance is directly influenced by the adder cells employed, for multipliers designed using adders; therefore power dissipation problem can be solved by exploring and using better adder designs. In this paper various full adder designs are analyzed in terms of delay, power consumption and area, As the adder block is prime concern for array multiplier in order to propose an efficient Multiplier architecture. The design and implementation of full adder cells and multiplier is performed on CADENCE design suite at GPDK 180 nm technology. The CMOS, GDI and Optimized full adder design is employed to implement array multiplier.