Critical path tracing in sequential circuits

Critical path tracing has been shown to be faster than traditional fault simulation methods, but it produces pessimistic results in some cases involving reconvergent fanout. It is shown that the pessimistic nature of critical path tracing in combinational circuits can lead to incorrect results that are not necessarily pessimistic in sequential circuits. A modification of the method for removing the approximation is proposed, and a critical path tracing algorithm for synchronous sequential circuits is presented.<<ETX>>

[1]  Vishwani D. Agrawal,et al.  A sequential circuit test generation using threshold-value simulation , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[2]  David T. Wang Properties of Faults and Criticalities of Values under Tests for Combinational Networks , 1975, IEEE Transactions on Computers.

[3]  P. R. Menon,et al.  Critical Path Tracing: An Alternative to Fault Simulation , 1984, IEEE Des. Test.

[4]  Douglas B. Armstrong,et al.  A Deductive Method for Simulating Faults in Logic Circuits , 1972, IEEE Transactions on Computers.

[5]  Melvin A. Breuer,et al.  Diagnosis and Reliable Design of Digital Systems , 1977 .