Area Recovery by Abutted Cell Placement: Can Fillers be Killers? An Eye-opening Viewpoint!

As the world is moving towards the UDSM era, designs are becoming more and more complex in terms of power, performance, area and time to market. Market demands and business competition is putting extreme pressure to devise unconventional methods for coming up with cost effective solutions without compromising on the needs. The need of the hour is to look at all the possible avenues to save cost and design time. The proposed approach is one step towards minimizing chip area wastage minimization due to inefficient placement algorithms. Contemporary placement algorithms often leave small gaps between standard cells in an attempt to limit density and ensure routability. In many cases these gaps can be consolidated by abutting the standard cells, creating additional useful area. We have found on many highly timing critical, congested and high cell row utilized designs (Row utilizations ~ 85%) the congested areas have small gaps between adjacent standard cells which gets eventually filled with small filler cells (FILLER1 and FILLER2) during filler insertion. These small filler cells serve no logical function whereas bigger FILLER cells can still be used later for the ECO/Metal ECO purposes. We have come up with the placement flows and scripts which minimize this area wastage due to small gaps between adjacent standard cells. This is achieved by removing the small fillers and then abutting standard cells to make bigger usable areas out of the small unusable areas. This bigger usable area is a boon to the designers during the design ECOs in the congested area. These bigger spaces are not only good for ECOs but also serve as a constructive area for reducing dynamic IR drops by filling with DECAP (decoupling capacitor) cells. This helps timing and power optimization in the congested area by serving as reinforcement to the power supply (Zhao et al., 2001). We found that designers could minimize the area wastage by more than 75-80% without significantly hurting the design timing or congestion statistics. Using the proposed, abutted standard cell placement flow helped in reducing the "Filler1-2/Total Filler" percentage by more than 75-80%. A few small filler cells are still used since they are under the metal 1-2 power route, where standard cells cannot be placed due the pin blockage issue for router access