Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing

Power and energy reduction is of uttermost importance for applications with stringent power/energy budget such as ultralow power and energy-harvested systems. Aggressive voltage scaling and in particular near-threshold computing is a promising approach to reduce the power and energy consumption. However, reducing the supply voltage leads to drastic performance variation induced by process and runtime variation. Temperature variation is one of the major sources of performance variation. In this paper, we study the impact of temperature variation on the circuit behavior in the near-threshold voltage region and show that the ambient temperature has a huge impact on the metrics such as circuit delay, power, and energy consumption. We also propose a low-cost, ambient temperature-aware voltage scaling technique to reduce the unnecessary energy overhead caused by temperature variation. Simulation results show that our proposed approach reduces the energy consumption by more than $1.95\times $ .

[1]  David Blaauw,et al.  Yield-Driven Near-Threshold SRAM Design , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Wei Hwang,et al.  Fully on-chip temperature, process, and voltage sensors , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[3]  Mehdi Baradaran Tahoori,et al.  Temperature-aware dynamic voltage scaling for near-threshold computing , 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

[4]  Jan M. Rabaey,et al.  Ultralow-Power Design in Near-Threshold Region , 2010, Proceedings of the IEEE.

[5]  Jacob A. Abraham,et al.  A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[6]  Sriram R. Vangal,et al.  A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor , 2014, 2014 IEEE International Conference on IC Design & Technology.

[7]  Xi Li,et al.  Temperature-aware energy minimization technique through dynamic voltage frequency scaling for embedded systems , 2010, 2010 2nd International Conference on Education Technology and Computer.

[8]  Bishop Brock,et al.  Active management of timing guardband to save energy in POWER7 , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[9]  S. Borkar,et al.  A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[10]  Uming Ko,et al.  A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[11]  Soraya Ghiasi,et al.  A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[12]  Miodrag Potkonjak,et al.  Maximizing yield in Near-Threshold Computing under the presence of process variation , 2013, 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

[13]  Mehdi Baradaran Tahoori,et al.  Variation-aware near threshold circuit synthesis , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[14]  David Blaauw,et al.  Reconfigurable energy efficient near threshold cache architectures , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[15]  Kaushik Roy,et al.  Device optimization for ultra-low power digital sub-threshold operation , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[16]  Chen-Chao Wang,et al.  Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[17]  Onodera Hidetoshi,et al.  Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design , 2015 .

[18]  Hu Chen,et al.  Opportunistic Turbo Execution in NTC: Exploiting the paradigm shift in performance bottlenecks , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[19]  David Blaauw,et al.  Timing yield enhancement through soft edge flip-flop based design , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[20]  Li Shang,et al.  Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[21]  David Blaauw,et al.  Ultralow-voltage, minimum-energy CMOS , 2006, IBM J. Res. Dev..

[22]  David Blaauw,et al.  Energy efficient near-threshold chip multi-processing , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[23]  Mark Anders,et al.  Near-threshold voltage (NTV) design — Opportunities and challenges , 2012, DAC Design Automation Conference 2012.

[24]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[25]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[26]  David Blaauw,et al.  Soft-edge flip-flops for improved timing yield: design and optimization , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[27]  Luca Benini,et al.  An Ambient Temperature Variation Tolerance Scheme for an Ultra Low Power Shared-L1 Processor Cluster , 2013, 2013 Euromicro Conference on Digital System Design.

[28]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[29]  David Money Harris,et al.  A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[30]  Bishop Brock,et al.  Active Guardband Management in Power7+ to Save Energy and Maintain Reliability , 2013, IEEE Micro.

[31]  Vanchinathan Venkataramani,et al.  Hierarchical power management for asymmetric multi-core in dark silicon era , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[32]  Massoud Pedram,et al.  Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[33]  Petru Eles,et al.  On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[34]  Nam Sung Kim,et al.  Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating , 2009, 2009 46th ACM/IEEE Design Automation Conference.