A dual-ported variable-way L1 D-cache design for high performance embedded DSP

This paper proposes a truly dual-ported variable-way set-associative L1 D-cache design for high performance embedded DSP (Digital Signal Processor). Several power-efficient D-cache optimizations are implemented in the design, which try to reduce the energy consumption of the L1 D-cache without affecting the performance significantly. The strategy to verify the L1 D-cache controller is also presented in this paper, which complements the simulation approach with the formal method by using System Verilog assertions. Experimental results show that miss rate of the L1 D-cache is about 5% better than that of a single-ported one due to dual-ported references. And, the miss penalty is improved by more than 20% compared with a baseline L1 D-cache without these optimizations.

[1]  Norman P. Jouppi,et al.  CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.

[2]  Fernando Gustavo Tinetti,et al.  Computer Architecture: A Quantitative Approach J. L. Hennessy, D. A. Patterson Morgan Kaufman, 4th Edition, 2007 , 2008 .

[3]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach, 5th Edition , 1996 .

[4]  Tadahiro Kuroda,et al.  Variable supply-voltage scheme for low-power high-speed CMOS digital design , 1998, IEEE J. Solid State Circuits.

[5]  Kanad Ghose,et al.  Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[6]  Michel Dubois,et al.  An Integrated Methodology for the Verification of Directory-Based Cache Protocols , 1994, 1994 International Conference on Parallel Processing Vol. 1.

[7]  Richard T. Witek,et al.  A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[8]  R. Stephany,et al.  A 200MHz 32b 0.5W CMOS RISC Microprocessor , 1998 .

[9]  M.A. Bayoumi,et al.  Variable-way set associative cache design for embedded system applications , 2003, 2003 46th Midwest Symposium on Circuits and Systems.