Deterministic Logic BIST for Transition Fault Testing

BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes is increased. Nevertheless, an extension to delay fault testing is not trivial, since this necessitates the application of pattern pairs. Consequently, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. In this paper, we consider the so-called transition fault model, which is widely used for complexity reasons. We present an extension of a DLBIST scheme for transition fault testing. Functional justification is used to generate the required pattern pairs. The efficiency of the extended scheme is investigated by using industrial benchmark circuits.

[1]  F. Brglez,et al.  On testability of combinational networks , 1984 .

[2]  Janak H. Patel,et al.  Enhanced delay defect coverage with path-segments , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[3]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[4]  Patrick Girard,et al.  An optimized BIST test pattern generator for delay testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[5]  Nur A. Touba,et al.  Altering a pseudo-random bit sequence for scan-based BIST , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[6]  Janak H. Patel,et al.  Segment delay faults: a new fault model , 1996, Proceedings of 14th VLSI Test Symposium.

[7]  Corot W. Starke,et al.  Built-In Test for CMOS Circuits , 1984, ITC.

[8]  Karl Fuchs,et al.  A BIST approach to delay fault testing with reduced test length , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[9]  Srinivas Patil,et al.  Broad-side delay test , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Edward J. McCluskey,et al.  TWO-PATTERN TEST CAPABILITIES OF AUTONOMOUS TPG CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[11]  Friedrich Hapke,et al.  Efficient pattern mapping for deterministic logic BIST , 2004 .

[12]  Irith Pomeranz,et al.  A scan BIST generation method using a markov source and partial bit-fixing , 2003, DAC '03.

[13]  Yervant Zorian,et al.  On the generation of pseudo-deterministic two-patterns test sequence with LFSRs , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[14]  H. Wunderlich,et al.  Bit-flipping BIST , 1996, ICCAD 1996.

[15]  I. Polian,et al.  A scalable BIST architecture for delay faults , 1999, European Test Workshop 1999 (Cat. No.PR00390).

[16]  B. Becker,et al.  Sequence Length , Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST , 2004 .

[17]  Stephen Pateras.  Achieving at-speed structural test , 2003, IEEE Design & Test of Computers.

[18]  Jacob Savir,et al.  On Random Pattern Test Length , 1984, IEEE Transactions on Computers.

[19]  Sandeep K. Gupta,et al.  BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms , 1996, IEEE Trans. Computers.

[20]  Jürgen Schlöffel,et al.  Synthesis of irregular combinational functions with large don't care sets , 2007, GLSVLSI '07.

[21]  Hans-Joachim Wunderlich.  PROTEST: A Tool for Probabilistic Testability Analysis , 1985, DAC 1985.

[22]  Nilanjan Mukherjee,et al.  A BIST scheme for the detection of path-delay faults , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[23]  Friedrich Hapke,et al.  Efficient pattern mapping for deterministic logic BIST , 2004, 2004 International Conferce on Test.

[24]  John A. Waicukauski,et al.  On computing the sizes of detected delay faults , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Jacob Savir.  Skewed-Load Transition Test: Part I, Calculus , 1992, Proceedings International Test Conference 1992.

[26]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[27]  Gary S. Ditlow,et al.  Random Pattern Testability , 1984, IEEE Transactions on Computers.