A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI

A 10-Gb/s SONET/SDH bit-error-rate monitoring LSI is fabricated by Si bipolar process. A byte-aligning demux architecture based on tree-type demux and clock inversions by detecting inversion indicating patterns reduces the power to only 14% of that of the previous chip. The LSI dissipates 0.6 W with -3.3-V supply voltage.

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