Parallel correlated double sampling technique for pipelined analogue-to-digital converters
暂无分享,去创建一个
A new correlated double sampling technique that avoids the additional thermal noise penalty is presented. The new technique employs a low-gain two-stage opamp with the second stage made up of multiple gain stages in parallel. The superior noise performance of the proposed technique to correlated double sampling is shown.
[1] Un-Ku Moon,et al. A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique , 2004, IEEE Journal of Solid-State Circuits.
[2] Jiri Vlach,et al. SWITCHED-CAPACITOR CIRCUITS WITH REDUCED SENSITIVITY TO FINITE AMPLIFIER GAIN. , 1986 .
[3] Kenneth L. Shepard,et al. High-throughput asynchronous datapath with software-controlled voltage scaling , 2004 .
[4] Jipeng Li,et al. A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique , 2004 .