VLSI implementation of multiple large template-based image matching for automatic target recognition

A special designed VLSI chip for template matching fundamentally used in automatic target recognition is proposed in this paper, it adopts normalized cross correlation algorithm. Parallelism inherent in the operation is explored to reduce the huge needed external bandwidth. As much as 8 large binary templates could be configured into four operation modes of eight 1-bit, four 2-bit, two 4-bit and one 8-bit templates using partial product scheme and they are processed in parallel. It takes 13.23ms to execute 120x160 template matching with 256x320 image, therefore is suitable for real-time applications. The prototype of the chip is emulated on FPGA and also synthesized with Design Compiler, die area is 3mm x 3.1mm and power consumption is 114.1 mw when operate at 108 MHz.

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