Design of Optimal Multiplierless FIR Filters
暂无分享,去创建一个
[1] Lars Wanhammar,et al. An MILP Approach for the Design of Linear-Phase FIR Filters with Minimum Number of Signed-Power-of-Two Terms , 2001 .
[2] Dong Shi,et al. Design of Discrete-Valued Linear Phase FIR Filters in Cascade Form , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] D. Kodek. Design of optimal finite wordlength FIR digital filters using integer programming techniques , 1980 .
[4] Arda Yurdakul,et al. An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[5] Mathias Faust,et al. Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[6] A. Antoniou. Digital Signal Processing: Signals, Systems, and Filters , 2005 .
[7] Qiang Zhang,et al. A Novel Hybrid Monotonic Local Search Algorithm for FIR Filter Coefficients Optimization , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[8] Dusan M. Kodek,et al. LLL Algorithm and the Optimal Finite Wordlength FIR Design , 2012, IEEE Transactions on Signal Processing.
[9] R. Hartley. Subexpression sharing in filters using canonic signed digit multipliers , 1996 .
[10] Yong Ching Lim,et al. Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[11] Dusan M. Kodek. Length limit of optimal finite wordlength FIR filters , 2013, Digit. Signal Process..
[12] J. Marques de Sa. A new design method of optimal finite wordlength linear phase FIR digital filters , 1983 .
[13] Silviu-Ioan Filip,et al. A Robust and Scalable Implementation of the Parks-McClellan Algorithm for Designing FIR Filters , 2016, ACM Trans. Math. Softw..
[14] H. Samueli,et al. An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients , 1989 .
[15] David Bull,et al. Genetic synthesis of reduced complexity filters and filter banks using primitive operator directed graphs , 2000 .
[16] Y. Lim,et al. FIR filter design over a discrete powers-of-two coefficient space , 1983 .
[17] Andrew G. Dempster,et al. Transition analysis on FPGA for multiplier-block based FIR filter structures , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).
[18] Markus Püschel,et al. Multiplierless multiple constant multiplication , 2007, TALG.
[19] O. Gustafsson,et al. Towards optimal multiple constant multiplication: A hypergraph approach , 2008, 2008 42nd Asilomar Conference on Signals, Systems and Computers.
[20] K. Steiglitz,et al. Some complexity issues in digital signal processing , 1984 .
[21] Ya Jun Yu,et al. Design of Low-Power Multiplierless Linear-Phase FIR Filters , 2017, IEEE Access.
[22] Dusan M. Kodek. Performance limit of finite wordlength FIR digital filters , 2005, IEEE Transactions on Signal Processing.
[23] A. Dempster,et al. Use of minimum-adder multiplier blocks in FIR digital filters , 1995 .
[24] Dong Shi,et al. Design of Extrapolated Impulse Response FIR Filters With Residual Compensation in Subexpression Space , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[25] A. Prasad Vinod,et al. On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[26] Peter Zipf,et al. FIR filter optimization for video processing on FPGAs , 2013, EURASIP J. Adv. Signal Process..
[27] A. W. M. van den Enden,et al. Discrete Time Signal Processing , 1989 .
[28] In-Cheol Park,et al. FIR filter synthesis algorithms for minimizing the delay and the number of adders , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[29] Andrew G. Dempster,et al. Designing multiplier blocks with low logic depth , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[30] A.V. Oppenheim,et al. Analysis of linear digital networks , 1975, Proceedings of the IEEE.
[31] Tapio Saramäki,et al. A systematic algorithm for the design of multiplierless FIR filters , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[32] Benjamin Müller,et al. The SCIP Optimization Suite 5.0 , 2017, 2112.08872.
[33] O. Gustafsson,et al. Design of linear-phase FIR filters combining subexpression sharing with MILP , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..
[34] Levent Aksoy,et al. Search algorithms for the multiple constant multiplications problem: Exact and approximate , 2010, Microprocess. Microsystems.
[35] Alireza Mehrnia,et al. Optimal Factoring of FIR Filters , 2015, IEEE Transactions on Signal Processing.
[36] Nicolas Brisebarre,et al. A Lattice Basis Reduction Approach for the Design of Finite Wordlength FIR Filters , 2018, IEEE Transactions on Signal Processing.
[37] Yong Ching Lim,et al. Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space , 2010, Circuits Syst. Signal Process..
[38] Ya Jun Yu,et al. Novel Structure for Area-Efficient Implementation of FIR Filters , 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.
[39] Y. Lim. Design of discrete-coefficient-value linear phase FIR filters with optimum normalized peak ripple magnitude , 1990 .
[40] Ya Jun Yu,et al. A polynomial-time algorithm for the design of multiplierless linear-phase FIR filters with low hardware cost , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).
[41] Martin Kumm,et al. Optimal Constant Multiplication Using Integer Linear Programming , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.
[42] Martin Kumm. Multiple constant multiplication optimizations for field programmable gate arrays , 2016 .
[43] Christoph Quirin Lauter,et al. Reliable Verification of Digital Implemented Filters Against Frequency Specifications , 2017, 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH).
[44] A. Dempster,et al. Constant integer multiplication using minimum adders , 1994 .
[45] Dong Shi,et al. Design of Linear Phase FIR Filters With High Probability of Achieving Minimum Number of Adders , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.
[46] Peter Zipf,et al. ScaLP: A Light-Weighted (MI)LP-Library , 2018, MBMV.
[47] Ya Jun Yu,et al. Bit-Level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[48] Andrew G. Dempster,et al. Power analysis of multiplier blocks , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[49] Oscar Gustafsson,et al. A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[50] L. Rabiner,et al. Analysis of quantization errors in the direct form for finite impulse response digital filters , 1973 .