Hardware and Software Co-design: An Architecture Proposal for a Network-on-Chip Switch based on Bufferless Data Flow

Abstract The use of on chip networks as interconnection media for systems implemented in FPGAs is limited by the amount of logical resources necessary to deploy the network in the target device, and the time necessary to adjust the network parameters to achieve the performance goal for the system. In this paper we present a switch architecture, with data flow control based on circuit switching and aimed for on-chip networks with a Spidergon topology, which seeks to reduce the area occupied without severely affecting the overall network performance. As a result, we obtained a switch that requires only 114 slices in its most economic version on a Virtex 4-device. We also provide a performance profile, obtained by subjecting a network formed by these switches to different synthetic workloads within a simulator. This simulator was developed as part of the design flow of the switch, and it proves to be an essential tool for the test and validation process.

[1]  Philippe Martin,et al.  Network-on-chip: the intelligence is in the wire , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[2]  Brent Nelson,et al.  PNoC: a flexible circuit-switched NoC for FPGA-based systems , 2006 .

[3]  Wim Vanderbauwhede,et al.  Quarc: A Novel Network-On-Chip Architecture , 2008, 2008 14th IEEE International Conference on Parallel and Distributed Systems.

[4]  Camel Tanougast,et al.  CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[5]  Jürgen Teich,et al.  DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[6]  Bin Liu,et al.  Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[7]  P. Armbruster,et al.  SpaceWire: a spacecraft onboard network for real-time communications , 2005, 14th IEEE-NPSS Real Time Conference, 2005..

[8]  O. Tayan,et al.  Networks-on-Chip: Challenges, trends and mechanisms for enhancements , 2009, 2009 International Conference on Information and Communication Technologies.

[9]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[10]  Matt Weisfeld,et al.  The Object-Oriented Thought Process , 2000 .

[11]  Mark Lutz,et al.  Learning Python: Powerful Object-Oriented Programming , 2008 .

[12]  Miltos D. Grammatikakis,et al.  Design of Cost-Efficient Interconnect Processing Units , 2008 .

[13]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[14]  Ali Ahmadinia,et al.  Dynamic interconnection of reconfigurable modules on reconfigurable devices , 2005, IEEE Design & Test of Computers.

[15]  Saurabh Dighe,et al.  The 48-core SCC Processor: the Programmer's View , 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.

[16]  Thilo Pionteck,et al.  Applying Partial Reconfiguration to Networks-On-Chips , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[17]  Harald Michalik,et al.  SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications , 2008, 2008 NASA/ESA Conference on Adaptive Hardware and Systems.