Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs

Current trend on FPGAs is to increase the number of inputs of the LUT up to six inputs to improve resource utilization. In this work we have analyzed the impact of the inputs expansion in two different architectures, memory-based and multiplexer-based, considering area, performance and power. A new memory-based architecture is presented based on the use of a 7-transistor cell and dedicated reading and writing circuits. The experimental results carried out demonstrate that for a six input LUT, our architecture outperforms the traditional multiplexer-based LUT, which is commonly considered the optimum architecture.