On Implementing Addition in VLSI Technology

Abstract In this paper we discuss the rules for evaluation of arithmetic algorithms based on the speed of their VLSI implementations. We present the rules which are simple enough to be useful for quick estimates, but yet reflect basic dependencies. By applying these rules we derived a simple scheme for VLSI implementation of addition (ALU), with a near minimal number of gates and small and regular area. Despite its simplicity, this scheme outperforms carry-lookahead and recurrence solver schemes as demonstrated by simulation of the actual implementation of examples. This is because the properties of the scheme are based on the dependencies and assumptions reflecting the real conditions existing in VLSI-CMOS technology. We discuss these results and demonstrate by actual implementation of examples that the measures based on the number of logic levels are not applicable to the new VLSI technologies.

[1]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[2]  R. Montoye,et al.  Automatically generated area, power and delay optimized ALUs , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  Daniel E. Atkins,et al.  A comparison of ALU structures for VLSI technology , 1983, 1983 IEEE 6th Symposium on Computer Arithmetic (ARITH).

[4]  David L. Kuck,et al.  The Structure of Computers and Computations , 1978 .

[5]  Daniel Gajski,et al.  Automatic Generation of Cells for Recurrence Structures , 1981, 18th Design Automation Conference.

[6]  Vojin G. Oklobdzija,et al.  Some optimal schemes for ALU implementation in VLSI technology , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

[7]  Daniel Gajski,et al.  A Heuristic for Suffix Solutions , 1986, IEEE Transactions on Computers.

[8]  T. Kilburn,et al.  Parallel addition in digital computers: a new fast 'carry' circuit , 1959 .

[9]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[10]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[11]  Mary Jane Irwin,et al.  Regular, area-time efficient carry-lookahead adders , 1985, IEEE Symposium on Computer Arithmetic.

[12]  Steven P. Levitan,et al.  VLSI DESIGN OF HIGH-SPEED, LOW-AREA ADDITION CIRCUITRY. , 1987 .

[13]  Tack-Don Han,et al.  Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[14]  M. Lehman,et al.  Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units , 1961, IRE Trans. Electron. Comput..

[15]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[16]  Shmuel Winograd,et al.  On the Time Required to Perform Addition , 1965, JACM.