Si n-TFETs on ultra thin body with suppressed ambipolarity

This paper presents an ultra thin body Si n-TFET which exploits a multi-finger gate layout and steep junction formed by dopant implantation into silicide (IIS) process. The sub-threshold slope (SS) reaches a minimum value of about 45 mV/dec, average SS of <;60mV/dec and 71mV/dec over one and three decades of drain current, respectively. A remarkable high Ion/Ioff ratio (~109) is achieved due to the successfully suppressed ambipolar behavior by the asymmetric source and drain design.

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