Performance assessment of different Network-on-Chip topologies

Multiprocessor System-on-Chip platforms are gaining prominence in the field of SoC design, which accommodates several large heterogeneous semiconductor intellectual property (IP) blocks, integrated onto a single chip. However, there's a crisis of global interconnection with existing bus architectures in such SoC Designs. In response to this crisis, Network-on-Chip (NoC) is an upcoming paradigm, and is becoming the leading contender to replace the conventional bus architectures. Many Network-on-Chip topologies have been proposed in an attempt to tackle various chip architecture needs and routing techniques. In this paper, some of the topologies such as Mesh, Torus, Binary Tree and Butterfly Fat Tree (BFT) have been simulated using a Network Simulator (NS2) and their performances have been assessed and compared taking throughput, maximum end-to-end latency and dropping probability as assessment parameters.

[1]  Shekhar Y. Borkar,et al.  Design perspectives on 22nm CMOS and beyond , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[2]  Radu Marculescu,et al.  Key research problems in NoC design: a holistic perspective , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[3]  K. K. Mahapatra,et al.  Design and analysis of five port router for network on chip , 2012, 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics.

[4]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[5]  Yi-ran Sun Simulation and Performance Evaluation for Networks on Chip , 2001 .

[6]  Partha Pratim Pande,et al.  Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[7]  Sao-Jie Chen,et al.  Networks on Chips: Structure and Design Methodologies , 2012, J. Electr. Comput. Eng..

[8]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[9]  Teerawat Issariyakul,et al.  Introduction to Network Simulator NS2 , 2008 .

[10]  Jörg Henkel,et al.  AdNoC: Runtime Adaptive Network-on-Chip Architecture , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[12]  Siti Aisah Network-on-chip mesh topology modeling and performance analysis , 2009 .

[13]  P. Cochat,et al.  Et al , 2008, Archives de pediatrie : organe officiel de la Societe francaise de pediatrie.

[14]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.