A novel 10T SRAM cell for low power circuits

This paper presents on the analysis of static and dynamic power dissipations in the proposed 10T SRAM cell. In the proposed structure two voltage sources, one connected with the Bit line and the other connected with the Bit bar line for reducing the voltage swing during the switching activity. This reduction in voltage swing causes less dynamic power dissipation during switching activity. Two stack transistors are also connected in the pull-down paths which result in increase in the threshold voltage of the transistors and thus cause the reduction in static power dissipation. Simulation has been done in 90nm CMOS technology with 1 volt power supply in Microwind 3.1 software. Simulation results have been compared with those of other existing SRAM cells.

[1]  Magdy A. Bayoumi,et al.  Novel 7T sram cell for low power cache design , 2005, Proceedings 2005 IEEE International SOC Conference.

[2]  Christian Piguet.  Low-Power Processors and Systems on Chips , 2005 .

[3]  Dhiraj K. Pradhan,et al.  A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[4]  Yen-Jen Chang,et al.  A New SRAM Cell Design for Both Power and Performance Efficiency , 2009, 2009 IEEE International Workshop on Memory Technology, Design, and Testing.

[5]  Vasily G. Moshnyaga,et al.  Low-Power Cache Design , 2018, Low-Power Processors and Systems on Chips.

[6]  Magdy A. Bayoumi,et al.  Low-Power Cache Design Using 7T SRAM Cell , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Lee-Sup Kim,et al.  A low-power SRAM using hierarchical bit line and local sense amplifiers , 2005, IEEE Journal of Solid-State Circuits.

[8]  Chia-Lin Yang,et al.  Zero-aware asymmetric SRAM cell for reducing cache power in writing zero , 2004, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Yngvar Berg,et al.  New SRAM design using body bias technique for ultra low power applications , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[10]  Shunsuke Okumura,et al.  A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme , 2009, 2009 10th International Symposium on Quality Electronic Design.

[11]  Lawrence T. Clark,et al.  Leakage Controlled Read Stable Static Random Access Memories , 2008, J. Comput..

[12]  Jason Schlessman,et al.  Accuracy-aware SRAM: A reconfigurable low power SRAM architecture for mobile multimedia applications , 2009, 2009 Asia and South Pacific Design Automation Conference.

[13]  Jaume Segura,et al.  Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[14]  Kaushik Roy,et al.  Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective , 2010, Proceedings of the IEEE.