Circular bist testing the digital logic within a high speed serdes
暂无分享,去创建一个
[1] Jacob Savir,et al. Built In Test for VLSI: Pseudorandom Techniques , 1987 .
[2] C.E. Stroud,et al. Automated BIST for sequential logic synthesis , 1988, IEEE Design & Test of Computers.
[3] N. Touba. Obtaining high fault coverage with circular BIST via state skipping , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[4] C.E. Stroud,et al. Reducing the cost of circular built-in self-test by selective flip-flop replacement , 1995, Conference Record AUTOTESTCON '95. 'Systems Readiness: Test Technology for the 21st Century'.
[5] Paolo Prinetto,et al. Circular Self-Test Path for FSMs , 1996, IEEE Des. Test Comput..
[6] Robert Gage. Structured CBIST in ASICS , 1993, Proceedings of IEEE International Test Conference - (ITC).
[7] Ah-Lyan Yee,et al. An integratable 1-2.5 Gbps low jitter CMOS transceiver with built in self test capability , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
[8] Andrzej Krasniewski,et al. Circular Self-Test Path: A Low-Cost BIST Technique , 1987, 24th ACM/IEEE Design Automation Conference.
[9] Janusz Rajski,et al. Logic BIST for large industrial designs: real issues and case studies , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).