A Dual-mode Pseudorandom number generator extension for ASIP design

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module ideal for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS structure, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare’s Processor Designer and synthesized into the Dong-bo 0.18㎛ CMOS cell library using the Synopsys Design compiler. With the proposed pseudorandom generator module, random number generation performance was 3.06 times faster, but the area increased only 2.004%.