A worst case timing analysis technique for multiple-issue machines
暂无分享,去创建一个
[1] Sang Lyul Min,et al. An Accurate Worst Case Timing Analysis for RISC Processors , 1995, IEEE Trans. Software Eng..
[2] Alan C. Shaw,et al. Reasoning About Time in Higher-Level Language Software , 1989, IEEE Trans. Software Eng..
[3] Richard M. Karp,et al. A characterization of the minimum cycle mean in a digraph , 1978, Discret. Math..
[4] Joe D. Warren,et al. The program dependence graph and its use in optimization , 1987, TOPL.
[5] Trung A. Diep,et al. VMW: A Visualization-Based Microarchitecture Workbench , 1995, Computer.
[6] Sharad Malik,et al. Cache modeling for real-time software: beyond direct mapped instruction caches , 1996, 17th IEEE Real-Time Systems Symposium.
[7] David B. Whalley,et al. Bounding worst-case instruction cache performance , 1994, 1994 Proceedings Real-Time Systems Symposium.
[8] David B. Whalley,et al. Integrating the timing analysis of pipelining and instruction caching , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.
[9] David A. Patterson,et al. Computer Architecture - A Quantitative Approach, 5th Edition , 1996 .
[10] Thomas R. Gross,et al. Postpass Code Optimization of Pipeline Constraints , 1983, TOPL.
[11] Mike Johnson,et al. Superscalar microprocessor design , 1991, Prentice Hall series in innovative technology.
[12] Gerry Kane,et al. MIPS RISC Architecture , 1987 .