An Echo-Canceller-Iess NFIC- TSV Hybrid 3D Interconnect for Simultaneous Bidirectional Vertical Communication

This paper presents an echo-canceller-less wireless-wireline hybrid 3D interconnect for simultaneous bidirectional (SBD) vertical communication. This is accomplished by combining wireless near-field inductive coupling channel (NFIC) that encompasses wireline through-silicon via (TSV) channels to form a bidirectional vertical link for the first time using face-to-back 3D integration technologies applicable for multi-layer vertical communication. In experimental demonstration, the transceiver simultaneously communicates at an effective data rate of 6 Gb/s consuming 290 fJ/bit over the NFIC and TSV channels in 65nm CMOS process. The developed hybrid interconnect architecture exhibits more than $\pmb{ 2\times}$ improved link performance over state-of-the-art 3D SBD link.

[1]  Yong Liu,et al.  A compact low-power 3D I/O in 45nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[2]  Pawan Agarwal,et al.  Current reuse triple-band signal source for multi-band wireless network-on-chip , 2017, 2017 IEEE MTT-S International Microwave Symposium (IMS).

[3]  Partha Pratim Pande,et al.  Energy and area efficient near field inductive coupling: A case study on 3D NoC , 2017, 2017 Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

[4]  Tadahiro Kuroda,et al.  Analytical thruchip inductive coupling channel design optimization , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

[5]  Tadahiro Kuroda,et al.  A 1 TB/s 1 pJ/b 6.4 ${\rm mm}^{2}/{\rm TB/s}$ QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[6]  Hsien-Hsin S. Lee,et al.  3D-MAPS: 3D Massively parallel processor with stacked memory , 2012, 2012 IEEE International Solid-State Circuits Conference.

[7]  Eby G. Friedman,et al.  Three-dimensional Integrated Circuit Design , 2008 .

[8]  B.A. Wooley,et al.  An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[9]  Pawan Agarwal,et al.  A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[10]  Gyung-Su Byun,et al.  A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication , 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[11]  Tony Tae-Hyoung Kim,et al.  A 3-Gb/s/ch Simultaneous Bidirectional Capacitive Coupling Transceiver for 3DICs , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Jason Cong,et al.  An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression , 2012, 2012 IEEE International Solid-State Circuits Conference.