论文信息 - On-package decoupling optimization with package macromodels

On-package decoupling optimization with package macromodels

Suppressing clock-gating-induced noise at the chip-package interface is one of the most challenging power distribution integrity issues. In this paper, accurate and efficient assessment of the effectiveness of on-package decoupling is facilitated by package macromodels which compactly represent packaging parasitics among multiple on-package decoupling and on-chip ports. Based on such assessment, a simulated-annealing-based optimization procedure is developed with the goal of finding the most cost-effective on-package decoupling while meeting the noise budget.

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