Entwurf eines Systems zur Positionsbestimmung auf Basis von Entfernungsmessungen zu Referenzpunkten

Zusammenfassung — Im Rahmen der Arbeiten wurde ein Algorithmus zur initialen Bestimmung und Verfolgung der Position von mobilen Netzwerkknoten erarbeitet und implementiert. Das Verfahren basiert auf Entfernungsinformationen zwischen mobilen und ortsfesten Knoten. Es wird ein zweistufiger Ansatz verfolgt. In einem ersten Schritt wird die Position des zu lokalisierenden Knotens durch mindestens drei (2D) bzw. vier (3D) Entfernungswerte zu Knoten mit bekannter Position, sogenannten Anker-Knoten, bestimmt. Auf Basis dieser Position erfolgt im zweiten Schritt die Verfolgung des mobilen Knotens mittels Kalmanfilter. Der Algorithmus wurde mit Hilfe eines Netzwerksimulators in einem realen Kommunikationsszenario verifiziert.

[1]  Andrzej Jaszkiewicz,et al.  Genetic local search for multi-objective combinatorial optimization , 2022 .

[2]  Christian Steger,et al.  High level fault injection for attack simulation in smart cards , 2004, 13th Asian Test Symposium.

[3]  F. ElGuibaly,et al.  A quantitative study for Java microprocessor architectural requirements. Part I: Instruction set design , 2000, Microprocess. Microsystems.

[4]  Behzad Razavi.  CMOS technology characterization for analog and RF design , 1999 .

[5]  Michael Wooldridge,et al.  Intelligent Agents: The Key Concepts , 2001, Multi-Agent-Systems and Applications.

[6]  Mohamed I. Elmasry,et al.  Optimizing CMOS implementations of the C-element , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[7]  David Christopher Moore.  Robust distribution sensor network localization with noisy range measurements , 2005 .

[8]  K.-Q. Luc,et al.  A high performance dataflow processor for multiprocessor systems , 1988, [1988] Proceedings. Workshop on the Future Trends of Distributed Computing Systems in the 1990s.

[9]  R. Bryant,et al.  Verification of Arithmetic Functions with Binary Moment Diagrams , 1994 .

[10]  Xavier Gandibleux,et al.  A survey and annotated bibliography of multiobjective combinatorial optimization , 2000, OR Spectr..

[11]  Renate Merker,et al.  Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints , 2006, Euro-Par.

[12]  Luigi Carro,et al.  A VLIW low power Java processor for embedded applications , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[13]  Heinrich Theodor Vierhaus,et al.  Perspectives of combining online and offline test technology for dependable systems on a chip , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

[14]  K. Arabi,et al.  Design for testability of embedded integrated operational amplifiers , 1998, IEEE J. Solid State Circuits.

[15]  Uli Kutter,et al.  Literatur. , 1941, Subjekt.

[16]  David Hardin.  Real-time objects on the bare metal: an efficient hardware realization of the Java/sup TM/ Virtual Machine , 2001, Fourth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing. ISORC 2001.

[17]  J. V. D. Berg.  The most general framework of continuous Hopfield neural networks , 1996 .

[18]  Jason R. Andrews.  Co-verification of Hardware and Software for ARM SoC Design , 2004 .

[19]  A. Varga,et al.  THE OMNET++ DISCRETE EVENT SIMULATION SYSTEM , 2003 .

[20]  Allen Ka,et al.  Design and Implementation of an Indoor Mobile Navigation System , 2002 .

[21]  Arthur C. Graesser,et al.  Is it an Agent, or Just a Program?: A Taxonomy for Autonomous Agents , 1996, ATAL.

[22]  Julio A. de Oliveira Filho,et al.  Efficient Mapping and Functional Verification of Parallel Algorithms on a MultiüContext Reconfigurable Architecture , 2007 .

[23]  N. Seifert,et al.  Timing vulnerability factors of sequentials , 2004, IEEE Transactions on Device and Materials Reliability.

[24]  J J Hopfield,et al.  Neurons with graded response have collective computational properties like those of two-state neurons. , 1984, Proceedings of the National Academy of Sciences of the United States of America.

[25]  V. Jerinić,et al.  Safe integration of parameterized IP , 2004, Integr..

[26]  Stuart Sutherland.  The Verilog PLI Is Dead (maybe) Long Live The SystemVerilog DPI , 2004 .

[27]  George Economakos,et al.  A cache based stack folding technique for high performance Java processors , 2006, JTRES '06.

[28]  Bruce A. Draper,et al.  Mapping a Single Assignment Programming Language to Reconfigurable Systems , 2002, The Journal of Supercomputing.

[29]  Ulrich Heinkel,et al.  Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing , 2004, CF '04.

[30]  Kin F. Li,et al.  A quantitative study for Java microprocessor architectural requirements. Part II: high-level language support , 2000, Microprocess. Microsystems.

[31]  William J. Dally,et al.  Register organization for media processing , 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

[32]  Christian Hochberger,et al.  The AMIDAR Class of Reconfigurable Processors , 2005, The Journal of Supercomputing.

[33]  Silvio Misera,et al.  Hardwarenahe Fehlersimulation mit effektiven SystemC-Modellen , 2007, MBMV.

[34]  Steffen Köhler,et al.  Design space exploration of coarse-grain reconfigurable DSPs , 2005, 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05).

[35]  V. T. Rajan,et al.  The Metronome: A Simpler Approach to Garbage Collection in Real-Time Systems , 2003, OTM Workshops.

[36]  Jacob A. Abraham,et al.  A novel functional test generation method for processors using commercial ATPG , 1997, Proceedings International Test Conference 1997.

[37]  Tim Menzies,et al.  What Is an Agent and Why Should I Care? , 2002, FAABS.

[38]  Vijay Pitchumani,et al.  ANSA: a new neural net based scheduling algorithm for high level synthesis , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[39]  Fabrizio Ferrandi,et al.  Error simulation based on the SystemC design description language , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[40]  Youngsoo Kim,et al.  Designing real-time H.264 decoders with dataflow architectures , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[41]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[42]  Robert Baumann,et al.  Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.

[43]  Alan Gray,et al.  picoArray technology: the tool's story , 2005, Design, Automation and Test in Europe.

[44]  Nicholas R. Jennings,et al.  A Roadmap of Agent Research and Development , 2004, Autonomous Agents and Multi-Agent Systems.

[45]  Jürgen Teich,et al.  An Architecture Description Language for Massively Parallel Processor Architectures , 2006, MBMV.

[46]  Theo Ungerer,et al.  Asynchrony in Parallel Computing: From Dataflow to Multithreading , 2001, Scalable Comput. Pract. Exp..

[47]  Jack Donovan,et al.  SystemC: From the Ground Up , 2004 .

[48]  Stefan Fricke,et al.  Werkzeuggestützte Entwicklung kooperativer Agenten im Dienstkontext , 2000 .

[49]  Rolf Drechsler,et al.  K*BMDs: a new data structure for verification , 1996, Proceedings ED&TC European Design and Test Conference.

[50]  Koen Langendoen,et al.  Distributed localization in wireless sensor networks: a quantitative compariso , 2003, Comput. Networks.

[51]  Alberto L. Sangiovanni-Vincentelli,et al.  Mixed signal design space exploration through analog platforms , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[52]  Kazuyoshi Takagi,et al.  An application specific Java processor with reconfigurabilities , 2000, ASP-DAC '00.

[53]  F. Leyn,et al.  An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[54]  Frank Vahid,et al.  Using on-chip configurable logic to reduce embedded system software energy , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[55]  Darrell Whitley,et al.  A genetic algorithm tutorial , 1994, Statistics and Computing.

[56]  Martin Schoeberl,et al.  JOP: A Java Optimized Processor for Embedded Real-Time Systems , 2008 .

[57]  Johan Karlsson,et al.  Fault injection into VHDL models: the MEFISTO tool , 1994 .

[58]  Peter Pirsch,et al.  Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications , 1999, J. VLSI Signal Process..

[59]  Pedro Larrañaga,et al.  Genetic Algorithms for the Travelling Salesman Problem: A Review of Representations and Operators , 1999, Artificial Intelligence Review.

[60]  V. T. Rajan,et al.  A real-time garbage collector with low overhead and consistent utilization , 2003, POPL '03.

[61]  Ieee Standard Test Access Port and Boundary-scan Architecture Ieee-sa Standards Board , 2001 .

[62]  Michael Nicolaidis,et al.  Embedded robustness IPs for transient-error-free ICs , 2002, IEEE Design & Test of Computers.

[63]  A. Ziv,et al.  Off-The-Shelf Vs . Custom Made Coverage Models , Which Is The One for You ? , 1998 .

[64]  Pedro J. Gil,et al.  Comparison and application of different VHDL-based fault injection techniques , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[65]  Frank Yellin,et al.  The Java Virtual Machine Specification , 1996 .

[66]  S. N. K. Watt,et al.  Artificial Societies and Psychological Agents , 1997, Software Agents and Soft Computing.

[67]  Adit D. Singh,et al.  Testability evaluation of sequential designs incorporating the multi-mode scannable memory element , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[68]  Renate Merker,et al.  Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism , 2006, 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

[69]  Daniel Gajski,et al.  Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[70]  Michael Wooldridge,et al.  Agents as a Rorschach Test: A Response to Franklin and Graesser , 1996, ATAL.

[71]  H. P. Tuinhout,et al.  Accurate capacitor matching measurements using floating gate test structures , 1995, Proceedings International Conference on Microelectronic Test Structures.

[72]  Martin Schoeberl,et al.  WCET analysis for a Java processor , 2006, JTRES '06.

[73]  Ulrich Heinkel,et al.  Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks , 2005, ReCoSoC.

[74]  Hyacinth S. Nwana,et al.  An Introduction to Agent Technology , 1997, Software Agents and Soft Computing.

[75]  Kong-Pang Pun,et al.  A low power asynchronous Java processor for contactless smart card , 2004 .

[76]  Luigi Carro,et al.  Making Java Work for Microcontroller Applications , 2001, IEEE Des. Test Comput..

[77]  Stephan Henker,et al.  Pulsed Multi-Layered Image Filtering: A VLSI Implementation , 2008 .

[78]  Avi Ziv,et al.  Hole analysis for functional coverage data , 2002, DAC '02.

[79]  Jörg P. Müller,et al.  The Design of Intelligent Agents , 1996, Lecture Notes in Computer Science.

[80]  Christian Hochberger,et al.  Hardware based online profiling in AMIDAR processors , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[81]  J. Michael O'Connor,et al.  picoJava-I: the Java virtual machine in hardware , 1997, IEEE Micro.

[82]  Tariq Samad,et al.  High-order Hopfield and Tank optimization networks , 1990, Parallel Comput..

[83]  Andy J. Wellings,et al.  Ravenscar‐Java: a high‐integrity profile for real‐time Java , 2002, JGI '02.

[84]  Henk Corporaal.  Microprocessor architectures - from VLIW to TTA , 1997 .

[85]  Jason R. Andrews.  Hardware/Software Co-Verification , 2005 .

[86]  J. Schemmel,et al.  Wafer-scale VLSI implementations of pulse coupled neural networks , 2007 .

[87]  E.M. Clarke,et al.  Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[88]  Krzysztof Kuchcinski,et al.  Automatic generation of application-specific systems based on a micro-programmed Java core , 2005, SAC '05.

[89]  Yousef Saad,et al.  Iterative methods for sparse linear systems , 2003 .

[90]  U. Heinkel,et al.  SystemC-AMS Assisted Design of an Inertial Navigation System , 2007, IEEE Sensors Journal.

[91]  Why Java.  High performance Java on embedded devices , 2007 .

[92]  Uwe Brinkschulte,et al.  Real-Time Garbage Collection for a Multithreaded Java Microcontroller , 2004, Real-Time Systems.

[93]  Giovanni Squillero,et al.  Fully automatic test program generation for microprocessor cores , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[94]  Andreas Kuehlmann,et al.  Formal verification of a PowerPC microprocessor , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[95]  Enrico Macii,et al.  Algebraic decision diagrams and their applications , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[96]  Lizy Kurian John,et al.  Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements , 2003, IEEE Trans. Computers.

[97]  Ramesh Radhakrishnan,et al.  Improving Java performance using hardware translation , 2001, ICS '01.

[98]  T.W. Matthews,et al.  A simulation method for accurately determining DC and dynamic offsets in comparators , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

[99]  Adit D. Singh,et al.  A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing , 1999, J. Electron. Test..

[100]  Greg Welch,et al.  SCAAT: incremental tracking with incomplete information , 1997, SIGGRAPH.

[101]  Mike O'Connor,et al.  PicoJava: A Direct Execution Engine For Java Bytecode , 1998, Computer.

[102]  Bruno Legeard,et al.  Boundary coverage criteria for test generation from formal models , 2004, 15th International Symposium on Software Reliability Engineering.

[103]  Rajeev Alur,et al.  An Analyser for Mesage Sequence Charts , 1996, TACAS.

[104]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[105]  H. Tsukioka,et al.  Reconfigurable synchronized dataflow processor , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[106]  R. Douglas,et al.  A Quantitative Map of the Circuit of Cat Primary Visual Cortex , 2004, The Journal of Neuroscience.

[107]  Yoshiyasu Takefuji,et al.  A neural network based algorithm for the scheduling problem in high-level synthesis , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[108]  Mario Schölzel,et al.  DESCOMP: A New Design Space Exploration Approach , 2005, ARCS.

[109]  D. Richard Kuhn,et al.  Pseudo-Exhaustive Testing for Software , 2006, 2006 30th Annual IEEE/NASA Software Engineering Workshop.

[110]  Uwe Eckhardt,et al.  Hierarchical algorithm partitioning at system level for an improved utilization of memory structures , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[111]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[112]  Nobu Matsumoto,et al.  A new verification methodology for complex pipeline behavior , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[113]  Petru Eles,et al.  System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search , 1997, Des. Autom. Embed. Syst..

[114]  Hari Balakrishnan,et al.  Tracking moving devices with the cricket location system , 2004, MobiSys '04.

[115]  Jürgen Becker,et al.  Multi-grained reconfigurable datapath structures for online-adaptive reconfigurable hardware architectures , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

[116]  Martin Schoeberl.  A Time Predictable Java Processor , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[117]  Giovanni Squillero,et al.  On the test of microprocessor IP cores , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[118]  Mehrdad Tamiz,et al.  Multi-objective meta-heuristics: An overview of the current state-of-the-art , 2002, Eur. J. Oper. Res..

[119]  Vlado Handziski,et al.  A Mobility Framework for OMNeT , 2003 .

[120]  N. Seifert,et al.  Robust system design with built-in soft-error resilience , 2005, Computer.

[121]  Stephan Henker,et al.  Mapping Complex, Large – Scale Spiking Networks on Neural VLSI , 2007 .

[122]  Michael Wooldridge,et al.  Introduction to multiagent systems , 2001 .

[123]  Shakir Ahmed Abbas.  Substrate current-a device and process monitor , 1974 .

[124]  Nikil D. Dutt,et al.  SPARK: a high-level synthesis framework for applying parallelizing compiler transformations , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[125]  Steve Furber.  ARM System-on-Chip Architecture , 2000 .

[126]  Ramesh Radhakrishnan,et al.  Allowing for ILP in an embedded Java processor , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[127]  Jan Langer,et al.  New Methods and Coverage Metrics for Functional Verification , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[128]  Chris Nappi,et al.  Scan vs. functional testing - a comparative effectiveness study on Motorola's MMC2107/sup TM/ , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[129]  J. J. Hopfield,et al.  “Neural” computation of decisions in optimization problems , 1985, Biological Cybernetics.

[130]  Jürgen Becker,et al.  Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics , 2005, ReCoSoC.

[131]  Ingolf Krüger,et al.  Distributed system design with message sequence charts , 2000 .

[132]  Gary B. Lamont,et al.  Multiobjective Evolutionary Algorithms: Analyzing the State-of-the-Art , 2000, Evolutionary Computation.

[133]  Kin F. Li,et al.  Adapting Tomasulo's algorithm for bytecode folding based Java processors , 2001, CARN.