A parallel router based on load-balanced region partition strategy
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[1] Wei Dong,et al. WavePipe: Parallel transient simulation of analog and digital circuits on multi-core shared-memory machines , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[2] Mehdi R. Zargham. Parallel channel routing , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[3] Sartaj Sahni,et al. Maze Routing on a Hypercube Multiprocessor Computer , 1987, International Conference on Parallel Processing.
[4] Yici Cai,et al. Congestion-driven W-shape multilevel full-chip routing framework , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[5] R. E. Massara,et al. A VLSI routing framework for use on a multiprocessor workstation , 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.
[6] Hao Sun,et al. Global routing for VLSI standard cells , 2004, Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513).
[7] Pinaki Mazumder. Parallel VLSI-routing models for polymorphic processors array , 1997 .
[8] Mikael Palczewski. Plane parallel A* maze router and its application to FPGAs , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.