Scheduling for functional pipelining and loop winding

We present an algorithm for pipelining loop execution in the presence of loop carried dependences. We optimize both the initiationinterval and the turnaroundtime of a schedule. Given const~aints on the number of functional units and buses, we 6rst determine an initiation interval and then incrementally partition the operations into blocks to fit into the execution windows. A refinement procedure is incorporated to improve the turn around time. The novel feature which differs our approach from others is that the scheduled operations are iteratively moved up and down to accommodate the ready yet unscheduled operations. The algorithm produces very encourageous results.

[1]  Peter B. Denyer,et al.  A new approach to pipeline optimisation , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[2]  Alice C. Parker,et al.  Sehwa: a software package for synthesis of pipelines from behavioral specifications , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Albert E. Casavant,et al.  Scheduling and hardware sharing in pipelined data paths , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[4]  Joos Vandewalle,et al.  An efficient microcode compiler for application specific DSP processors , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[6]  Monica Sin-Ling Lam,et al.  A Systolic Array Optimizing Compiler , 1989 .

[7]  Yu-Chin Hsu,et al.  Optimum and heuristic data path scheduling under resource constraints , 1991, DAC '90.

[8]  E. F. Girczyc,et al.  Loop winding--a data flow approach to functional pipelining , 1987 .

[9]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Alexandru Nicolau,et al.  Percolation based synthesis , 1991, DAC '90.

[11]  Mohamed I. Elmasry,et al.  Architectural synthesis for DSP silicon compilers , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Ronald Gary Cytron Compile-time scheduling and optimization for asynchronous machines (multiprocessor, compiler, parallel processing) , 1984 .

[13]  Alexander Aiken,et al.  Optimal loop parallelization , 1988, PLDI '88.