Design of a Tunable Differential Ring Oscillator With Short Start-Up and Switching Transients

Timing measurements such as jitter and skew in the range of picoseconds, for circuits with multigigahertz clocks or multigigabit-per-second serial communication interfaces are common. A Vernier-oscillator-based time-to-digital converter (TDC) is a circuit that allows picosecond-timing measurements by means of two tunable oscillators. In such a circuit, the oscillator jitter, tuning response, start-up transient, and frequency switching transient play an important role in the TDCs measurement time and accuracy. In this work, we discuss the design of an optimized, differential CML-based ring oscillator and its impact on a TDC design. Simulation results from the new oscillator show that the oscillator's short start-up and frequency switching transients have negligible effects on the accuracy of the TDC measurements. TDC simulation results show that, using two of these oscillators, accurate timing measurements in the range of 10 to 900 ps can be achieved with best-case accuracy of ~2 ps.

[1]  D. Porat,et al.  Review of Sub-Nanosecond Time-Interval Measurements , 1973 .

[2]  D. M. Santos,et al.  A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip , 1995, 1995 IEEE Nuclear Science Symposium and Medical Imaging Conference Record.

[3]  Abhijit Chatterjee,et al.  A high-resolution jitter measurement technique using ADC sampling , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[4]  A.K.M. Kamruzzaman Mollah Design of a tunable CML-based differential ring oscillator with short start-up and switching transiets , 2004 .

[5]  조성환,et al.  High resolution time-to-digital converter , 2006 .

[6]  S. Tabatabaei,et al.  Jitter generation and measurement for test of multi-Gbps serial IO , 2004 .

[7]  J. Kalisz,et al.  Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution , 1997 .

[8]  J. Everard Low noise oscillators , 1992, 1992 IEEE Microwave Symposium Digest MTT-S.

[9]  Sassan Tabatabaei-Zavareh Embedded test circuits and methodologies for mixed-signal ICs , 2000 .

[10]  André Ivanov,et al.  Embedded timing analysis: a soc infrastructure , 2002, IEEE Design & Test of Computers.

[11]  Gordon W. Roberts,et al.  A high-resolution flash time-to-digital converter and calibration scheme , 2004, 2004 International Conferce on Test.

[12]  Takahiro J. Yamaguchi,et al.  A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[13]  Donald Barry Carlin Time interval measurements using mode locked lasers , 1977 .

[14]  S. F. Dow,et al.  A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip , 1995 .

[15]  Gordon W. Roberts,et al.  A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).