Post-bond test of Through-Silicon Vias with open defects

Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent failure mechanism affecting TSVs. Although there is considerable research effort dedicated to improve TSVs testing, no much attention has been paid to weak defects, especially to weak open defects (resistive opens) causing small delays. In this work, a testing strategy is proposed to detect small delay defects by means of a post-bond oscillation test. Variations in the Duty Cycle of transmitted signals after unbalanced logic gates are shown to detect weak open defects in TSVs. HSPICE simulations including process parameter variations show the effectiveness of the method in the detection of weak open defects above 1 kΩ.

[1]  Hsien-Hsin S. Lee,et al.  Test Challenges for 3D Integrated Circuits , 2009, IEEE Design & Test of Computers.

[2]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[3]  TingTing Hwang,et al.  TSV redundancy: Architecture and design issues in 3D IC , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[4]  Ding-Ming Kwai,et al.  On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification , 2009, 2009 Asian Test Symposium.

[5]  Paul D. Franzon,et al.  Through Silicon Via(TSV) defect/pinhole self test circuit for 3D-IC , 2009, 2009 IEEE International Conference on 3D System Integration.

[6]  William R. Bottoms.  Test challenges for 3D integration (an invited paper for CICC 2011) , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[7]  Krishnendu Chakrabarty,et al.  Pre-bond probing of TSVs in 3D stacked ICs , 2011, 2011 IEEE International Test Conference.

[8]  R. Suaya,et al.  Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs , 2010, IEEE Transactions on Electron Devices.

[9]  Erik Jan Marinissen,et al.  On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs , 2010, 2010 IEEE International Test Conference.

[10]  Fangming Ye,et al.  TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation , 2012, DAC Design Automation Conference 2012.

[11]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.

[12]  Ding-Ming Kwai,et al.  On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding , 2010, 2010 28th VLSI Test Symposium (VTS).

[13]  Sung Kyu Lim,et al.  Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[14]  Zhihong Huang,et al.  Electromigration of Cu-Sn-Cu micropads in 3D interconnect , 2008, 2008 58th Electronic Components and Technology Conference.

[15]  Joungho Kim,et al.  High-frequency through-silicon Via (TSV) failure analysis , 2011, 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems.

[16]  Chun-Lung Hsu,et al.  Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

[17]  Erik Jan Marinissen,et al.  Testing TSV-based three-dimensional stacked ICs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[18]  Fan Zhang,et al.  Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods , 2012, J. Electron. Test..

[19]  Shi-Yu Huang,et al.  Performance Characterization of TSV in 3D IC via Sensitivity Analysis , 2010, 2010 19th IEEE Asian Test Symposium.

[20]  Luca Benini,et al.  A low-overhead fault tolerance scheme for TSV-based 3D network on chip links , 2008, ICCAD 2008.

[21]  C. Sharbono,et al.  Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking , 2006, 56th Electronic Components and Technology Conference 2006.

[22]  W. Dehaene,et al.  Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs , 2010, IEEE Transactions on Electron Devices.

[23]  Shi-Yu Huang,et al.  In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Shi-Yu Huang,et al.  Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.