AN ALGEBRA FOR SYSTOLIC COMPUTATION

Publisher Summary This chapter presents the algebra for systolic computation. Many systolic algorithms have been proposed as solutions to computation-bound problems. By exploiting the regularity and parallelism inherent to given problems and by employing high degrees of parallelism and pipelining, systolic algorithms implemented in very-large-scale integration achieve high performance with regular communication structures and low input/output requirements. A number of prototype machines for implementing systolic algorithms, ranging from single-purpose chips, through application-oriented yet programmable systems, to general systems with reconfigurable interconnections, have been designed and built. Building-block chips for systolic architectures have also been proposed or designed, including the CMU programmable systolic chip. Instead of suggesting methods for deriving or verifying systolic designs, algebra is presented in the chapter for manipulating algorithm designs for VLSI implementation in general. With this algebra, a designer is able to manipulate designs by pushing symbols, to conveniently meet desirable design criteria such as locality and regularity of data communication.

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