A 1-V 13-mW Single-Path Frequency-Translating $\Delta \Sigma $ Modulator With 55-dB SNDR and 4-MHz Bandwidth at 225 MHz

This paper presents a frequency-translating bandpass ΔΣ modulator that uses single-path mixing within the ΔΣ feedback loop to downconvert a 4-MHz signal band from IF<sub>1</sub> = 225 MHz at the input to IF<sub>2</sub> = 25 MHz at the output. The proposed ΔΣ modulator is designed with a sixth-order continuous-time loop filter and a 3-bit quantizer. The quantizer operates at a sampling frequency of 100 MHz, which is lower than IF<sub>1</sub> and, therefore, reduces both the power consumption and the sensitivity to timing errors relative to a conventional bandpass ΔΣ modulator. Furthermore, the loop filter implements noise shaping primarily at IF <sub>2</sub>, which reduces the sensitivity to coefficient variations. The prototype chip was fabricated in 65-nm CMOS with an active area of 0.55 mm<sup>2</sup>. It achieves an SNDR of 55 dB over a 4-MHz signal bandwidth, and consumes 13 mW from a 1-V power supply.

[1]  Jan Craninckx,et al.  A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz bandwidth 2.4 GHz RF bandpass ΔΣ ADC in 40 nm CMOS , 2010, 2010 IEEE Radio Frequency Integrated Circuits Symposium.

[2]  H. Aboushady,et al.  Using finite impulse response feedback DACs to design /spl Sigma//spl Delta/ modulators based on LC filters , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

[3]  Kimmo Koli,et al.  A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[4]  J. M. Khoury,et al.  A 400-Ms/s frequency translating bandpass sigma-delta modulator , 1999, IEEE J. Solid State Circuits.

[5]  Richard Schreier,et al.  A 375-mW quadrature bandpass ΔΣ ADC with 8.5-MHz BW and 90-dB DR at 44 MHz , 2006 .

[6]  Anas A. Hamoui,et al.  Design Constraints for Image-Reject Frequency-Translating $\Delta\Sigma$ Modulators , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  R. Schreier,et al.  Mismatch shaping for a current-mode multibit delta-sigma DAC , 1999, IEEE J. Solid State Circuits.

[8]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[9]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[10]  Jonathan Borremans,et al.  A 2.4 GHz Low-Power Sixth-Order RF Bandpass $\Delta\Sigma$ Converter in CMOS , 2009, IEEE Journal of Solid-State Circuits.

[11]  William B. Kuhn,et al.  Bandpass /spl Sigma//spl Delta/ modulator employing undersampling of RF signals for wireless communication , 2000 .

[12]  R. T. Baird,et al.  Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging , 1995 .

[13]  Mohammad Taherzadeh-Sani,et al.  A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS , 2011, IEEE Journal of Solid-State Circuits.

[14]  W. Snelgrove,et al.  Excess loop delay in continuous-time delta-sigma modulators , 1999 .

[15]  Un-Ku Moon,et al.  A time-delay jitter-insensitive continuous-time bandpass ΔΣ modulator architecture. , 2005 .

[16]  Thomas Blon,et al.  A 20-mW 640-MHz CMOS continuous-time ΣΔ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB , 2006 .

[17]  Chih-Kong Ken Yang,et al.  A 14-bit, 10-Msamples/s D/A converter using multibit /spl Sigma//spl Delta/ modulation , 1999 .

[18]  B. Wooley,et al.  A 14-bit , 10-Msamples / s D / A Converter Using Multibit Modulation , 1998 .

[19]  Ahmed Ashry,et al.  A 4th order subsampled RF ∑Δ ADC centered at 2.4GHz with a sine-shaped feedback DAC , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

[20]  R. Schreier,et al.  A 375-mW Quadrature Bandpass $\Delta\Sigma$ ADC With 8.5-MHz BW and 90-dB DR at 44 MHz , 2006, IEEE Journal of Solid-State Circuits.

[21]  Joseph Mitola,et al.  The software radio architecture , 1995, IEEE Commun. Mag..

[22]  C. Holuigue,et al.  A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.

[23]  Richard Schreier.  HIGH-SPEED BANDPASS ADCs , 2006 .

[24]  Sebastian Hoyos,et al.  A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth , 2010, IEEE Journal of Solid-State Circuits.

[25]  Susan Luschas,et al.  Radio frequency digital-to-analog converter , 2004, IEEE Journal of Solid-State Circuits.

[26]  H. Aboushady,et al.  Using Finite Impulse Response Feedback DACs to design Σ∆ modulators based on LC filters. , 2005 .

[27]  Anas A. Hamoui,et al.  Design Constraints for Image-Reject Frequency-Translating ΔΣ Modulators , 2009 .

[28]  Omid Shoaei,et al.  A multi-feedback design for LC bandpass delta-sigma modulators , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[29]  Saska Lindfors,et al.  80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers , 2003 .

[30]  W. Snelgrove,et al.  Clock jitter and quantizer metastability in continuous-time delta-sigma modulators , 1999 .

[31]  A. Namdar,et al.  A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside a sigma-delta modulator loop , 1999 .

[32]  Un-Ku Moon,et al.  A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[33]  Michael P. Flynn,et al.  A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF , 2014, IEEE Journal of Solid-State Circuits.

[34]  Roubik Gregorian,et al.  Introduction to CMOS OP-AMPs and Comparators , 1999 .