A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp

Scaling in CMOS technologies has made the application of traditional opamp topologies increasingly difficult. In the face of decreasing voltage headroom and intrinsic device gain, designers have employed techniques such as gain-boosting, correlated double sampling , and correlated level-shifting (CLS) [1] to maximize output swing for a given gain specification. Zero-crossing based circuits (ZCBC) remove the opamp altogether and use a comparator and current sources [2], which are more amenable to scaling and have proven capable of high efficiency, as in [3]. However, the open loop nature of ZCBC creates challenges for designs that must reliably track over process, voltage, and temperature. In this paper, we describe a hybrid CLS-opamp/ZCBC pipelined ADC that introduces techniques to improve accuracy, robustness, and power efficiency in scaled technologies. It incorporates CLS and a low power, small output swing double-cascoded telescopic opamp to achieve very high effective gain. A dynamically biased zero-crossing detector (ZCD) is introduced that increases the power efficiency of ZCBC designs.