Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs
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Andrew R. Brown | A. Asenov | J. H. Davies | S. Kaya | G. Slavcheva | A. Brown | J. Davies
[1] Irene A. Stegun,et al. Handbook of Mathematical Functions. , 1966 .
[2] Frank Stern,et al. Polarizability of a Two-Dimensional Electron Gas , 1967 .
[3] C. Mead,et al. Fundamental limitations in microelectronics—I. MOS technology , 1972 .
[4] J. R. Brews,et al. Surface Potential Fluctuations Generated by Interface Charge Inhomogeneities in MOS Devices , 1972 .
[6] R. W. Keyes,et al. Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics , 1975 .
[7] J. R. Brews,et al. Carrier‐density fluctuations and the IGFET mobility near threshold , 1975 .
[8] J. R. Brews,et al. Theory of the carrier‐density fluctuations in an IGFET near threshold , 1975 .
[9] R.W. Keyes,et al. Physical limits in digital electronics , 1975, Proceedings of the IEEE.
[10] F. Stern,et al. Electronic properties of two-dimensional systems , 1982 .
[11] R. Howard,et al. Discrete Resistance Switching in Submicrometer Silicon Inversion Layers: Individual Interface Traps and Low-Frequency ( 1 f ?) Noise , 1984 .
[12] Ferry,et al. Surface roughness at the Si(100)-SiO2 interface. , 1985, Physical review. B, Condensed matter.
[13] K. R. Lakshmikumar,et al. Characterisation and modeling of mismatch in MOS transistors for precision analog design , 1986 .
[14] A. R. Wazzan,et al. MOS (Metal Oxide Semiconductor) Physics and Technology , 1986 .
[15] Risto M. Nieminen,et al. Electronic Properties of Two-Dimensional Systems , 1988 .
[16] M. J. Kirton,et al. Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/ƒ) noise , 1989 .
[17] G. Iafrate,et al. Quantum correction to the equation of state of an electron gas in a semiconductor. , 1989, Physical review. B, Condensed matter.
[18] P.K. Ko,et al. Random telegraph noise of deep-submicrometer MOSFETs , 1990, IEEE Electron Device Letters.
[19] Davies,et al. Potential fluctuations in heterostructure devices. , 1990, Physical review. B, Condensed matter.
[20] J. Davies,et al. Potential Fluctuations in Heterostructure Devices , 1990 .
[21] Potential fluctuations due to the randomly distributed charges at the semiconductor-insulator interface in MIS-structures , 1991 .
[22] Eddy Simoen,et al. Explaining the amplitude of RTS noise in submicrometer MOSFETs , 1992 .
[23] J. W. Park,et al. DRAM variable retention time , 1992, 1992 International Technical Digest on Electron Devices Meeting.
[24] William H. Press,et al. Numerical Recipes in Fortran 77 , 1992 .
[25] Naoyuki Shigyo,et al. Effects of microscopic fluctuations in dopant distributions on MOSFET threshold voltage , 1992 .
[26] Chenming Hu,et al. Impact of polysilicon depletion in thin oxide MOS technology , 1993, 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers.
[27] T. Mikolajick,et al. Influence of statistical dopant fluctuations on MOS transistors with deep submicron channel lengths , 1993 .
[28] H. Wong,et al. Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's , 1993, Proceedings of IEEE International Electron Devices Meeting.
[29] A. Toriumi,et al. Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .
[30] D. Burnett,et al. Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits , 1994, Proceedings of 1994 VLSI Technology Symposium.
[31] Michel Steyaert,et al. Threshold voltage mismatch in short-channel MOS transistors , 1994 .
[32] M. Dutoit,et al. Random telegraph signals in deep submicron n-MOSFET's , 1994 .
[33] John H. Davies,et al. The Smallest Electronic Device: An Electron Waveguide , 1994 .
[34] Tso-Ping Ma,et al. The impact of device scaling on the current fluctuations in MOSFET's , 1994 .
[35] Robert Sinclair,et al. Atomic-Order Planarization of Ultrathin SiO2/Si(001) Interfaces , 1994 .
[36] Roughness analysis of Si/SiGe heterostructures , 1995 .
[37] D. Schmitt-Landsiedel,et al. Intra-die device parameter variations and their impact on digital CMOS gates at low supply voltages , 1995, Proceedings of International Electron Devices Meeting.
[38] H. Iwai,et al. 1.5 nm direct-tunneling gate oxide Si MOSFET's , 1996 .
[39] P. Stolk,et al. The effect of statistical dopant fluctuations on MOS device performance , 1996, International Electron Devices Meeting. Technical Digest.
[40] K. Taniguchi,et al. Study of interface roughness dependence of electron mobility in Si inversion layers using the Monte Carlo method , 1996 .
[41] Gerard Morin,et al. MOSFET Matching in a Deep Submicron Technology , 1996, ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference.
[42] J. A. López-Villanueva,et al. Influence of mobility fluctuations on random telegraph signal amplitude in n-channel metal–oxide–semiconductor field-effect transistors , 1997 .
[43] K. Takeuchi,et al. Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[44] H. Wong,et al. CMOS scaling into the nanometer regime , 1997, Proc. IEEE.
[45] E. Worley,et al. The gate bias and geometry dependence of random telegraph signal amplitudes [MOSFET] , 1997, IEEE Electron Device Letters.
[46] M. R. Pinto,et al. Electron and hole quantization and their impact on deep submicron silicon p- and n-MOSFET characteristics , 1997 .
[47] D.B.M. Klaassen,et al. Device modeling of statistical dopant fluctuations in MOS transistors , 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.
[48] Karl Goser,et al. Matching analysis of deposition defined 50-nm MOSFET's , 1998 .
[49] D. Z.-Y. Ting,et al. Interface Roughness Effects in Ultra-Thin Tunneling Oxides , 1998, VLSI Design.
[50] Zhiping Yu,et al. Multi-dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-Level Programming Techniques , 1998 .
[51] D. Vasileska,et al. Modeling of deep-submicrometer MOSFETs: random impurity effects, threshold voltage shifts and gate capacitance attenuation , 1998, 1998 Sixth International Workshop on Computational Electronics. Extended Abstracts (Cat. No.98EX116).
[52] D. Macintyre,et al. Sub-35 nm metal gratings fabricated using PMMA with high contrast developers , 1998 .
[53] M. Schulz,et al. Random telegraph signal: An atomic probe of the local current in field-effect transistors , 1998 .
[54] Takahiro Matsuo,et al. Reduction of line edge roughness in the top surface imaging process , 1998 .
[55] A. Asenov. Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .
[56] Subhash Saini,et al. Hierarchical approach to "atomistic" 3-D MOSFET simulation , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[57] S. Saini,et al. Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m MOSFET's with epitaxial and /spl delta/-doped channels , 1999 .
[58] Jonathan L. Cobb,et al. Demonstration of pattern transfer into sub-100 nm polysilicon line/space features patterned with extreme ultraviolet lithography , 1999 .
[59] S. Saini,et al. Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0 . 1m MOSFET ’ s with Epitaxial and-Doped Channels , 1999 .
[60] M. Ieong,et al. Monte Carlo modeling of threshold variation due to dopant fluctuations , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
[61] M. Yoshizawa,et al. Resolution limiting mechanism in electron beam lithography , 2000 .
[62] Effect of single-electron interface trapping in decanano MOSFETs: A 3D atomistic simulation study , 2000 .
[63] Asen Asenov,et al. Random telegraph signal amplitudes in sub 100 nm (decanano) MOSFETs: a 3D 'Atomistic' simulation study , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[64] Effect of single-electron interface trapping in decanano MOSFETs : A 3 D atomistic simulation study , 2000 .
[65] Eric Cassan,et al. Calculation of direct tunneling gate current through ultra-thin oxide and oxide/nitride stacks in MOSFETs and H-MOSFETs , 2000 .
[66] A. Asenov,et al. Effect of oxide interface roughness on the threshold voltage fluctuations in decanano MOSFETs with ultrathin gate oxides , 2000, International Conference on Simulation of Semiconductor Processes and Devices.
[67] A. Pirovano,et al. On the correlation between surface roughness and inversion layer mobility in Si-MOSFETs , 2000, IEEE Electron Device Letters.
[68] S. Saini,et al. Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxide , 2000 .
[69] Toshiro Hiramoto,et al. Impact of the device scaling on the low-frequency noise in n-MOSFETs , 2000 .
[70] M. Ieong,et al. Modeling line edge roughness effects in sub 100 nanometer gate length devices , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).
[71] Karl Hess,et al. Simulation of Si-SiO/sub 2/ defect generation in CMOS chips: from atomistic structure to chip failure rates , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[72] Qi Xiang,et al. 15 nm gate length planar CMOS transistor , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[73] Andrew R. Brown,et al. Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study , 2001 .
[74] Wolfgang H. Krautschneider,et al. Observation and modeling of random telegraph signals in the gate and drain currents of tunneling metal–oxide–semiconductor field-effect transistors , 2001 .
[75] T. Ono,et al. Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current , 2001 .
[76] C.H. Diaz,et al. An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling , 2001, IEEE Electron Device Letters.
[77] Shaofeng Yu,et al. 3D Modelling of Fluctuation Effects in Highly Scaled VLSI Devices , 2001, VLSI Design.
[78] T. Kudo,et al. High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[79] D. Hisamoto. FD/DG-SOI MOSFET-a viable approach to overcoming the device scaling limit , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[80] M. Hussein,et al. An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[81] W. Fichtner,et al. Quantum device-simulation with the density-gradient model on unstructured grids , 2001 .
[82] Andrew R. Brown,et al. Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETs , 2001 .
[83] Petru Andrei,et al. Statistical analysis of semiconductor devices , 2001 .
[84] A. Asenov,et al. Integrated atomistic process and device simulation of decananometre MOSFETs , 2002, International Conferencre on Simulation of Semiconductor Processes and Devices.
[85] H. Tuinhout. Impact of Parametric Fluctuations on Performance and Yield of Deep-Submicron Technologies , 2002, 32nd European Solid-State Device Research Conference.
[86] Jason C. S. Woo,et al. Modeling and Analysis of Gate Line Edge Roughness Effect on CMOS Scaling Towards Deep Nanoscale Gate Length , 2002 .
[87] H. Nambu,et al. UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
[88] Yuan Taur,et al. Design considerations for CMOS near the limits of scaling , 2002 .
[89] Masami Hane,et al. 3D MOSFET simulation considering long-range Coulomb potential effects for analyzing statistical dopant-induced fluctuations associated with atomistic process simulator , 2002, International Conferencre on Simulation of Semiconductor Processes and Devices.
[90] J. Wu,et al. Transistor width dependence of LER degradation to CMOS device characteristics , 2002, International Conferencre on Simulation of Semiconductor Processes and Devices.
[91] A. Asenov,et al. Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations , 2002 .
[92] G. Knoblinger,et al. Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
[93] Andrew R. Brown,et al. Potential fluctuations in metal–oxide–semiconductor field-effect transistors generated by random impurities in the depletion layer , 2002 .
[94] Andrew R. Brown,et al. Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter , 2002 .
[95] Andrew R. Brown,et al. RTS amplitudes in decananometer MOSFETs: 3-D simulation study , 2003 .
[96] B. E. White,et al. Effects of dopant granularity on superhalo-channel MOSFETs according to two- and three-dimensional computer simulations , 2003 .
[97] A. Asenov,et al. Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .
[98] B. Krauskopf,et al. Proc of SPIE , 2003 .
[99] G. Ghibaudo,et al. The impact of short channel and quantum effects on the MOS transistor mismatch , 2003 .
[100] Aaas News,et al. Book Reviews , 1893, Buffalo Medical and Surgical Journal.