Signal integrity verification of coupled interconnect lines using efficient eye-diagram determination

An efficient signal integrity verification method of coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes. Then, bit blocks for coupled lines which are composed of the finite size of bits are represented with the fundamental modes. In addition, the crosstalk effects within the bit block are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are mathematically modeled, followed by analytical eye-diagram determination. It is shown that not only the proposed technique has excellent agreement with SPICE W-model-based simulation but also is it very computation-time-efficient, compared with SPICE simulation.

[1]  Chung-Kuan Cheng,et al.  Predicting and Optimizing Jitter and Eye-Opening Based on Bitonic Step Response , 2007, 2007 IEEE Electrical Performance of Electronic Packaging.

[2]  R. Montoye,et al.  Beyond Moore's Law: the interconnect era , 2004, Computing in Science & Engineering.

[3]  Joseph Fjelstad,et al.  3D PCB architecture for next generation high speed interconnections , 2005 .

[4]  Yi Zhu,et al.  Efficient and accurate eye diagram prediction for high speed signaling , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[5]  Ruey-Beei Wu,et al.  Fast Methodology for Determining Eye Diagram Characteristics of Lossy Transmission Lines , 2009, IEEE Transactions on Advanced Packaging.

[6]  Masanori Hashimoto,et al.  Performance limitation of on-chip global interconnects for high-speed signaling , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[7]  J.F. Buckwalter,et al.  Predicting Microwave Digital Signal Integrity , 2009, IEEE Transactions on Advanced Packaging.

[8]  Masanori Hashimoto,et al.  Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration , 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[9]  Masanori Hashimoto,et al.  Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[10]  Taehoon Kim,et al.  Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled $RLC$ Interconnect Lines , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Giovanni Campardo,et al.  Signal Integrity Flow for System-in-Package and Package-on-Package Devices , 2009, Proceedings of the IEEE.

[12]  Yu Hu,et al.  Worst case timing jitter and amplitude noise in differential signaling , 2009, 2009 10th International Symposium on Quality Electronic Design.

[13]  Mark Bohr,et al.  The new era of scaling in an SoC world , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.