Injecting multiple upsets in a SEU tolerant 8051 micro-controller

This paper investigates the behavior of a SEU tolerant 8051-like micro-controller protected by single error correction Hamming code in the presence of multiple upsets. Upsets were randomly injected in all sensitive parts of the design. The experiment was emulated in a Virtex FPGA platform. Results evaluate the robustness of the tolerant 8051 in a multiple upsets environment.

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