Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review

Recently, there have been many studies attempting to take advantage of advancements in Artificial Intelligence (AI) in Analog and Mixed-Signal (AMS) circuit design. Automated circuit sizing optimization and improving the accuracy of performance models are the two predominant uses of AI in AMS circuit design. This paper first introduces and explains the basic concepts in AI especially the ones that are more suitable to this application. Next, it surveys some recent studies of various AI techniques for AMS circuit design. Then, it discusses the main approaches as well as the pros and cons of each method. Finally, it gives meaningful insights about the current challenges and open issues, as well as recommends approaches for specific applications.

[1]  Xin Li,et al.  Finding deterministic solution from underdetermined equation: Large-scale performance modeling by least angle regression , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[2]  Wei Cai,et al.  Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Fan Yang,et al.  Efficient bit error rate estimation for high-speed link by Bayesian model fusion , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Yong Wang,et al.  An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design , 2013, DATE '13.

[6]  Yao-Wen Chang,et al.  Recent research development and new challenges in analog layout synthesis , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

[7]  Xuan Zeng,et al.  Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Hung-Ming Chen,et al.  Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping , 2011, 2011 12th International Symposium on Quality Electronic Design.

[9]  Carl E. Rasmussen,et al.  Gaussian processes for machine learning , 2005, Adaptive computation and machine learning.

[10]  David Z. Pan,et al.  S2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits , 2019, ASP-DAC.

[11]  Naveen Verma,et al.  A seizure-detection IC employing machine learning to overcome data-conversion and analog-processing non-idealities , 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

[12]  Philip S. Yu,et al.  A Comprehensive Survey on Graph Neural Networks , 2019, IEEE Transactions on Neural Networks and Learning Systems.

[13]  Trent McConaghy,et al.  High-dimensional statistical modeling and analysis of custom integrated circuits (invited paper) , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[14]  Ah Chung Tsoi,et al.  Face recognition: a convolutional neural-network approach , 1997, IEEE Trans. Neural Networks.

[15]  Georges G. E. Gielen,et al.  Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[16]  Sachin S. Sapatnekar,et al.  GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits , 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[17]  David Z. Pan,et al.  Machine Learning for Yield Learning and Optimization , 2018, 2018 IEEE International Test Conference (ITC).

[18]  Engin Afacan,et al.  Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test , 2021, Integr..

[19]  Petro Liashchynskyi,et al.  Grid Search, Random Search, Genetic Algorithm: A Big Comparison for NAS , 2019, ArXiv.

[20]  Saraju P. Mohanty,et al.  Exploring Kriging for Fast and Accurate Design Optimization of Nanoscale Analog Circuits , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[21]  Fan Yang,et al.  Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[22]  David Z. Pan,et al.  Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab Models , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[23]  Xin Li,et al.  Efficient hierarchical performance modeling for integrated circuits via Bayesian co-learning , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[24]  Xin Li,et al.  Finding Deterministic Solution From Underdetermined Equation: Large-Scale Performance Variability Modeling of Analog/RF Circuits , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  Ricardo Povoa,et al.  On the Exploration of Promising Analog IC Designs via Artificial Neural Networks , 2018, 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

[26]  Michiel Steyaert,et al.  Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[27]  Chenjie Gu,et al.  Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[28]  Nando de Freitas,et al.  Taking the Human Out of the Loop: A Review of Bayesian Optimization , 2016, Proceedings of the IEEE.

[29]  Xin Li,et al.  Efficient Hierarchical Performance Modeling for Analog and Mixed-Signal Circuits via Bayesian Co-Learning , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  Rafiqul Zaman Khan,et al.  Methods to Avoid Over-Fitting and Under-Fitting in Supervised Machine Learning (Comparative Study) , 2014 .

[31]  Mariusz Naumowicz,et al.  Technology migration of analogue CMOS circuits using hooke-jeeves algorithm and genetic algorithms in multi-core CPU systems , 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.

[32]  Colin Raffel,et al.  Exploring the Limits of Transfer Learning with a Unified Text-to-Text Transformer , 2019, J. Mach. Learn. Res..

[33]  Fan Yang,et al.  BMF-BD: Bayesian model fusion on Bernoulli distribution for efficient yield estimation of integrated circuits , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[34]  Francisco V. Fernández,et al.  Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[35]  Mark Po-Hung Lin,et al.  Classifying Analog and Digital Circuits with Machine Learning Techniques Toward Mixed-Signal Design Automation , 2018, 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

[36]  Lina Zhou,et al.  Movie Review Mining: a Comparison between Supervised and Unsupervised Classification Approaches , 2005, Proceedings of the 38th Annual Hawaii International Conference on System Sciences.

[37]  Lars Hedrich,et al.  Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts , 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

[38]  Pankaj P. Prajapati,et al.  Two stage CMOS operational amplifier design using particle swarm optimization algorithm , 2015, 2015 IEEE UP Section Conference on Electrical Computer and Electronics (UPCON).

[39]  Yoshua Bengio,et al.  Neural Machine Translation by Jointly Learning to Align and Translate , 2014, ICLR.

[40]  R. Tibshirani.  Regression Shrinkage and Selection via the Lasso , 1996 .

[41]  Glen Kramer,et al.  Application-specific worst case corners using response surfaces and statistical models , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[42]  Geoffrey E. Hinton,et al.  ImageNet classification with deep convolutional neural networks , 2012, Commun. ACM.

[43]  Anil K. Jain,et al.  Artificial Neural Networks: A Tutorial , 1996, Computer.

[44]  Yurong Liu,et al.  A survey of deep neural network architectures and their applications , 2017, Neurocomputing.

[45]  Ruoyu Li,et al.  Adaptive Graph Convolutional Neural Networks , 2018, AAAI.

[46]  Xuan Zeng,et al.  An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[47]  Wangyang Zhang,et al.  Large-scale statistical performance modeling of analog and mixed-signal circuits , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

[48]  Naveen Verma,et al.  Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[50]  Rob A. Rutenbar,et al.  Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[51]  Günhan Dündar,et al.  An evolutionary approach to automatic synthesis of high-performance analog integrated circuits , 2003, IEEE Trans. Evol. Comput..

[52]  Zheng Wang,et al.  Analog circuit optimization system based on hybrid evolutionary algorithms , 2009, Integr..

[53]  Wojciech Zaremba,et al.  Recurrent Neural Network Regularization , 2014, ArXiv.

[54]  Jean-Olivier Plouchart,et al.  Co-Learning Bayesian Model Fusion: Efficient performance modeling of analog and mixed-signal circuits using side information , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[55]  Georges G. E. Gielen,et al.  Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[56]  Bo Liu,et al.  Efficient global optimization of MEMS based on surrogate model assisted evolutionary algorithm , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[57]  Andreas Krause,et al.  Parallelizing Exploration-Exploitation Tradeoffs with Gaussian Process Bandit Optimization , 2012, ICML.

[58]  Fan Yang,et al.  Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[59]  Stephen P. Boyd,et al.  Optimization of phase-locked loop circuits via geometric programming , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[60]  Xin Yao,et al.  Model-based evolutionary algorithms: a short survey , 2018, Complex & Intelligent Systems.

[61]  A. Hajimiri,et al.  A fully-integrated self-healing power amplifier , 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

[62]  Saraju P. Mohanty,et al.  Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[63]  Elad Alon,et al.  BAG2: A process-portable framework for generator-based AMS circuit design , 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

[64]  R. Brereton,et al.  Support vector machines for classification and regression. , 2010, The Analyst.

[65]  D K Smith,et al.  Numerical Optimization , 2001, J. Oper. Res. Soc..

[66]  Alex Doboli,et al.  A low-voltage, low-power amplifier created by reasoning-based, systematic topology synthesis , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[67]  Xuan Zeng,et al.  FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp , 2013, 2013 IEEE 10th International Conference on ASIC.

[68]  Rob A. Rutenbar,et al.  Remembrance of circuits past: macromodeling by data mining in large analog design spaces , 2002, DAC '02.

[69]  Constantine Caramanis,et al.  Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[70]  Günhan Dündar,et al.  Artificial Neural Network Assisted Analog IC Sizing Tool , 2019, 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

[71]  J. V. Bannister.  Biosensors: Fundamentals and applications , 1987 .

[72]  Constantine Caramanis,et al.  Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[73]  Neil D. Lawrence,et al.  Batch Bayesian Optimization via Local Penalization , 2015, AISTATS.

[74]  Rob A. Rutenbar,et al.  Practical, fast Monte Carlo statistical static timing analysis: Why and how , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[75]  David Ginsbourger,et al.  Fast Computation of the Multi-Points Expected Improvement with Applications in Batch Selection , 2013, LION.

[76]  José Antonio Lozano,et al.  Sensitivity Analysis of k-Fold Cross Validation in Prediction Error Estimation , 2010, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[77]  Fred W. Glover,et al.  Tabu Search - Part I , 1989, INFORMS J. Comput..

[78]  Sylvain Bourdel,et al.  On the use of causal feature selection in the context of machine-learning indirect test , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[79]  R. Bharat Rao,et al.  Bayesian Co-Training , 2007, J. Mach. Learn. Res..

[80]  Rob A. Rutenbar,et al.  MAELSTROM: efficient simulation-based synthesis for custom analog cells , 1999, DAC '99.

[81]  Georges G. E. Gielen,et al.  An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[82]  Peter I. Frazier,et al.  The Parallel Knowledge Gradient Method for Batch Bayesian Optimization , 2016, NIPS.

[83]  Donald R. Jones,et al.  Global versus local search in constrained optimization of computer models , 1998 .

[84]  Song Han,et al.  Learning to Design Circuits , 2018, ArXiv.

[85]  David Blaauw,et al.  Fully-Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits , 2019 .

[86]  Georges G. E. Gielen,et al.  Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model , 2011, 2011 Design, Automation & Test in Europe.

[87]  Jung-Fa Tsai,et al.  A Review of Deterministic Optimization Methods in Engineering and Management , 2012 .

[88]  Rob A. Rutenbar,et al.  Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs , 2007, Proceedings of the IEEE.

[89]  Vladimir Stojanovic,et al.  Late Breaking Results: Analog Circuit Generator based on Deep Neural Network enhanced Combinatorial optimization , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[90]  Fred Glover,et al.  Tabu Search - Part II , 1989, INFORMS J. Comput..

[91]  G. Casella,et al.  Explaining the Gibbs Sampler , 1992 .

[92]  J. S. Rao,et al.  Spike and slab variable selection: Frequentist and Bayesian strategies , 2005, math/0505633.

[93]  Fan Yang,et al.  Efficient Bayesian yield optimization approach for analog and SRAM circuits , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[94]  Xuan Zeng,et al.  Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[95]  Keertana Settaluri,et al.  Fully Automated Analog Sub-Circuit Clustering with Graph Convolutional Neural Networks , 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[96]  Francisco V. Fernández,et al.  A memetic approach to the automatic design of high-performance analog integrated circuits , 2009, TODE.

[97]  Juan M. Gimenez,et al.  Prediction of wind pressure coefficients on building surfaces using artificial neural networks , 2018 .

[98]  Soumith Chintala,et al.  Unsupervised Representation Learning with Deep Convolutional Generative Adversarial Networks , 2015, ICLR.

[99]  Hong Zhang,et al.  Efficient design-specific worst-case corner extraction for integrated circuits , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[100]  Deli Zhao,et al.  Scalable Gaussian Process Regression Using Deep Neural Networks , 2015, IJCAI.

[101]  M. del Mar Hershenson.  Design of pipeline analog-to-digital converters via geometric programming , 2002 .

[102]  Stephen P. Boyd,et al.  Geometric programming for circuit optimization , 2005, ISPD '05.

[103]  Prabhat,et al.  Scalable Bayesian Optimization Using Deep Neural Networks , 2015, ICML.

[104]  Georges G. E. Gielen,et al.  GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[105]  Jasbir S. Arora,et al.  Survey of multi-objective optimization methods for engineering , 2004 .

[106]  Rob A. Rutenbar,et al.  Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[107]  Hazem M. Abbas,et al.  Chameleon ART: a non-optimization based analog design migration framework , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[108]  Donald R. Jones,et al.  Efficient Global Optimization of Expensive Black-Box Functions , 1998, J. Glob. Optim..

[109]  Revna Acar Vural,et al.  International Journal of Electronics and Communications (aeü) Analog Circuit Sizing via Swarm Intelligence , 2022 .

[110]  Philip N. Strenski,et al.  Gradient-based optimization of custom circuits using a static-timing formulation , 1999, DAC '99.

[111]  Dean Liu,et al.  A Framework for Designing Reusable Analog Circuits , 2003 .

[112]  Xin Li,et al.  Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[113]  Jan Van der Spiegel,et al.  GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[114]  Wangyang Zhang,et al.  Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression , 2010, Design Automation Conference.

[115]  Madhavan Swaminathan,et al.  Application of Machine Learning for Optimization of 3-D Integrated Circuits and Systems , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[116]  Xuan Zeng,et al.  A practical method for auto-design and optimization of DC-DC buck converter , 2013, 2013 IEEE 10th International Conference on ASIC.

[117]  Zoubin Ghahramani,et al.  Parallel Predictive Entropy Search for Batch Global Optimization of Expensive Objective Functions , 2015, NIPS.

[118]  An Open-source Framework for Autonomous SoC Design with Analog Block Generation , 2020, 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC).

[119]  Thomas Bäck,et al.  Evolutionary algorithms in theory and practice - evolution strategies, evolutionary programming, genetic algorithms , 1996 .

[120]  Ganapati Panda,et al.  A Multiobjective Optimization Based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO , 2014, IEEE Transactions on Semiconductor Manufacturing.

[121]  Arthur Nieuwoudt,et al.  Multi-level approach for integrated spiral inductor optimization , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[122]  Christofer Toumazou,et al.  The invention of CMOS amplifiers using genetic programming and current-flow analysis , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[123]  Matt J. Kusner,et al.  Bayesian Optimization with Inequality Constraints , 2014, ICML.

[124]  Georges G. E. Gielen,et al.  Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[125]  Hao Chen,et al.  Challenges and opportunities toward fully automated analog layout design , 2020 .

[126]  Ronald G. Dreslinski,et al.  3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology , 2019, 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[127]  Xuan Zeng,et al.  An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[128]  Radford M. Neal.  Pattern Recognition and Machine Learning , 2007, Technometrics.

[129]  Si Wu,et al.  Improving support vector machine classifiers by modifying kernel functions , 1999, Neural Networks.

[130]  Ngai Wong,et al.  Analog circuit design by nonconvex polynomial optimization: Two design examples , 2010, Int. J. Circuit Theory Appl..

[131]  Arthur E. Hoerl,et al.  Ridge Regression: Biased Estimation for Nonorthogonal Problems , 2000, Technometrics.

[132]  Xuan Zeng,et al.  Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[133]  David D. Wentzloff,et al.  A 152μW −99dBm BPSK/16-QAM OFDM Receiver for LPWAN Applications , 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[134]  Ranga Vemuri,et al.  Extraction and use of neural network models in automated synthesis of operational amplifiers , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[135]  Chenjie Gu,et al.  Bayesian Model Fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[136]  Fan Yang,et al.  Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design , 2018, ICML.

[137]  Mehryar Mohri,et al.  L2 Regularization for Learning Kernels , 2009, UAI.