A 2 $\times$ 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems

The world’s first 2 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 30k-spin multi-chip CMOS annealing processor (AP)—based on the processing-in-memory approach for solving large-scale combinatorial optimization problem—was developed. To expand the bit width of coefficients and enhance the scalability of the AP, it has three key features: an expandable and high-accuracy spin operator for local communication, a highly integrated spin circuit using direct access to SRAM, and a low-latency inter-chip interface that does not affect the runtime or results of the annealing process. The AP is fabricated on the basis of 40-nm CMOS technology. It was experimentally demonstrated that the spin-flip ratio of the processor agrees well with theoretical values based on the Gibbs distribution over a wide temperature range. As a result, under two-chip operation with 2 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 30k spins, the AP achieves an annealing time of 22 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>, which is 455 times and 2.6 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 10⁴ times faster than those achieved by our previous CMOS-AP and a conventional CPU, respectively. Moreover, its energy efficiency is 1.75 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 10⁵ times higher than that of a conventional CPU-based algorithm.