A study of arithmetic circuits and the effect of utilising Reed-Muller techniques.

Reed-Muller algebraic techniques, as an alternative means in logic design, became more attractive recently, because of their compact representations of logic functions and yielding of easily testable circuits. It is claimed by some researchers that ReedMuller algebraic techniques are particularly suitable for arithmetic circuits. In fact, no practical application in this field can be found in the open literature. This project investigates existing Reed-Muller algebraic techniques and explores their application in arithmetic circuits. The work described in this thesis is concerned with practical applications in arithmetic circuits, especially for minimizing logic circuits at the transistor level. These results are compared with those obtained using the conventional Boolean algebraic techniques. This work is also related to wider fields, from logic level design to layout level design in CMOS circuits, the current leading technology in VLSI. The emphasis is put on circuit level (transistor level) design. The results show that, although Boolean logic is believed to be a more general tool in logic design, it is not the best tool in all situations. Reed-Muller logic can generate good results which can't be easily obtained by using Boolean logic. F or testing purposes, a gate fault model is often used in the conventional implementation of Reed-Muller logic, which leads to Reed-Muller logic being restricted to using a small gate set. This usually leads to generating more complex circuits. When a cell fault model, which is more suitable for regular and iterative circuits, such as arithmetic circuits, is used instead of the gate fault model in ReedMuller logic, a wider gate set can be employed to realize Reed-Muller functions. As a result, many circuits designed using Reed-Muller logic can be comparable to that designed using Boolean logic. This conclusion is demonstrated by testing many randomly generated functions. The main aim of this project is to develop arithmetic circuits for practical application. A number of practical arithmetic circuits are reported. The first one is a carry chain adder. Utilising the CMOS circuit characteristics, a simple and high speed carry chain is constructed to perform the carry operation. The proposed carry chain adder can be reconstructed to form a fast carry skip adder, and it is also found to be a good application for residue number adders. An algorithm for an on-line adder and its implementation are also developed. Another circuit is a parallel multiplier based on 5:3 counter. The simulations show that the proposed circuits are better than many previous designs, in terms of the number of transistors and speed. In addition, a 4:2 compressor for a carry free adder is investigated. It is shown that the two main schemes to construct the 4:2 compressor have a unified structure. A variant of the Baugh and Wooley algorithm is also studied and generalized in this work.

[1]  David E. Muller,et al.  Application of Boolean algebra to switching circuit design and to error detection , 1954, Trans. I R E Prof. Group Electron. Comput..

[2]  Irving S. Reed,et al.  A class of multiple-error-correcting codes and the decoding scheme , 1954, Trans. IRE Prof. Group Inf. Theory.

[3]  T. Kilburn,et al.  A parallel arithmetic unit using a saturated-transistor fast-carry circuit , 1960 .

[4]  Jack Sklansky,et al.  Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..

[5]  A. Avizeinis,et al.  Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .

[6]  O. L. Macsorley.  High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.

[7]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[8]  Richard I. Tanaka,et al.  Residue arithmetic and its applications to computer technology , 1967 .

[9]  SUDHAKAR M. REDDY,et al.  Easily Testable Realizations ror Logic Functions , 1972, IEEE Transactions on Computers.

[10]  Bruce A. Wooley,et al.  A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.

[11]  Earl E. Swartzlander.  Parallel Counters , 1973, IEEE Transactions on Computers.

[12]  William J. Kubitz,et al.  A Compact High-Speed Parallel Multiplication Scheme , 1977, IEEE Transactions on Computers.

[13]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[14]  James E. Robertson,et al.  Logical design of a redundant binary adder , 1978, 1978 IEEE 4th Symposium onomputer Arithmetic (ARITH).

[15]  Jean-Pierre Deschamps,et al.  Discrete and switching functions , 1978 .

[16]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[17]  Takao Uehara,et al.  Optimal Layout of CMOS Functional Arrays , 1978, 16th Design Automation Conference.

[18]  Sudhakar M. Reddy,et al.  A Testable Design of Iterative Logic Arrays , 1981, IEEE Transactions on Computers.

[19]  Huey Ling.  High Speed Binary Adder , 1981, IBM J. Res. Dev..

[20]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[21]  Xia Chen,et al.  Mapping of Reed-Muller coefficients and the minimisation of exclusive OR-switching functions , 1982 .

[22]  P. Besslich.  Efficient computer method for ExOR logic design , 1983 .

[23]  Randal E. Bryant,et al.  A Switch-Level Model and Simulator for MOS Digital Systems , 1984, IEEE Transactions on Computers.

[24]  R. B. Urquhart,et al.  Systolic matrix and vector multiplication methods for signal processing , 1984 .

[25]  Joseph J. F. Cavanagh.  Digital Computer Arithmetic: Design And Implementation , 1984 .

[26]  Norman R. Scott.  Computer Number Systems and Arithmetic , 1984 .

[27]  A. K. Choudhury,et al.  Testable design of RMC networks with universal tests for detecting stuck-at and bridging faults , 1985 .

[28]  Min-You Wu,et al.  Invited paper A unified theory for MOS circuit design—switching network logic , 1985 .

[29]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[30]  R. Gnanasekaran,et al.  A Fast Serial-Parallel Binary Multiplier , 1985, IEEE Transactions on Computers.

[31]  Hiroto Yasuura,et al.  High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.

[32]  David H. Green,et al.  Modern logic design , 1986 .

[33]  A. Tran.  Graphical method for the conversion of minterms to Reed-Muller coefficients and the minimisation of exclusive-OR switching functions , 1987 .

[34]  N. Takagi,et al.  A high-speed multiplier using a redundant binary adder tree , 1987 .

[35]  Abhijit Chatterjee,et al.  TEST GENERATION FOR ARITHMETIC UNITS BY GRAPH LABELLING. , 1987 .

[36]  D. Y. Chen,et al.  A Design Rule Independent Cell Compiler , 1987, 24th ACM/IEEE Design Automation Conference.

[37]  Janak H. Patel,et al.  A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders , 1987, IEEE Transactions on Computers.

[38]  Lionel M. Ni,et al.  A Rule-Based Circuit Representation for Automated CMOS Design and Verification , 1987, 24th ACM/IEEE Design Automation Conference.

[39]  John P. Hayes,et al.  Layout Optimization of CMOS Functional Cells , 1987, 24th ACM/IEEE Design Automation Conference.

[40]  Tomás Lang,et al.  On-the-Fly Conversion of Redundant into Conventional Representations , 1987, IEEE Transactions on Computers.

[41]  Naofumi Takagi,et al.  Design of high speed MOS multiplier and divider using redundant binary representation , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[42]  Jean-Michel Muller,et al.  A Way to Build Efficient Carry-Skip Adders , 1987, IEEE Transactions on Computers.

[43]  Douglas A. Pucknell,et al.  Basic VLSI Design , 1987 .

[44]  Robert W. Doran.  Variants of an Improved Carry Look-Ahead Adder , 1988, IEEE Trans. Computers.

[45]  Marek A. Perkowski,et al.  A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms , 1988, DAC '88.

[46]  M. Perkowski,et al.  Minimization of multiple-valued input multi-output mixed-radix exclusive sums of products for incompletely specified Boolean functions , 1989, Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic.

[47]  Stamatis Vassiliadis,et al.  A General Proof for Overlapped Multiple-Bit Scanning Multiplications , 1989, IEEE Trans. Computers.

[48]  Randall L. Geiger,et al.  VLSI Design Techniques for Analog and Digital Circuits , 1989 .

[49]  Tri-state map for the minimisation of exclusive-OR switching functions , 1989 .

[50]  J. V. Salmon,et al.  Syntactic translation and logic synthesis in Gatemap , 1989 .

[51]  M. Karpovsky,et al.  Detection of stuck-at and bridging faults in Reed-Muller canonical (RMC) networks , 1989 .

[52]  Martine D. F. Schlag,et al.  Analysis and design of CMOS Manchester adders with variable carry-skip , 1989, Proceedings of 9th Symposium on Computer Arithmetic.

[53]  Kazuo Yano,et al.  A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic , 1990 .

[54]  Keshab K. Parhi,et al.  Digit-serial DSP architectures , 1990, [1990] Proceedings of the International Conference on Application Specific Array Processors.

[55]  Peter R. Cappello,et al.  Easily Testable Iterative Logic Arrays , 1990, IEEE Trans. Computers.

[56]  M. Perkowski,et al.  An exact algorithm to minimize mixed-radix exclusive sums of products for incompletely specified Boolean functions , 1990, IEEE International Symposium on Circuits and Systems.

[57]  J. M. Saul.  An improved algorithm for the minimization of mixed polarity Reed-Muller representations , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[58]  S. Bhatia,et al.  Testing of iterative logic arrays , 1990, Proceedings of the 33rd Midwest Symposium on Circuits and Systems.

[59]  T. Noguchi,et al.  A 15-ns 32*32-b CMOS multiplier with an improved parallel structure , 1990 .

[60]  Homayoon Sam,et al.  A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations , 1990, IEEE Trans. Computers.

[61]  T. N. Rajashekhara,et al.  Fast multiplier design using redundant signed-digit numbers , 1990 .

[62]  Tsutomu Sasao,et al.  On the complexity of mod-2l sum PLA's , 1990 .

[63]  B. Harking.  Efficient algorithm for canonical Reed-Muller expansions of Boolean functions , 1990 .

[64]  D. Green.  Reed-Muller canonical forms with mixed polarity and their manipulations , 1990 .

[65]  Tomás Lang,et al.  Fast Multiplication Without Carry-Propagate Addition , 1990, IEEE Trans. Computers.

[66]  M. Mehta,et al.  High-speed multiplier design using multi-input counter and compressor circuits , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

[67]  D. Green.  Families of Reed-Muller canonical forms , 1991 .

[68]  Jonathan Saul.  An algorithm for the multi-level minimization of Reed-Muller representations , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[69]  M. Dagenais.  Efficient algorithmic decomposition of transistor groups into series, bridge, and parallel combinations , 1991 .

[70]  Barrie Hayes-Gill,et al.  Novel cell architecture for bit level systolic arrays multiplication , 1991 .

[71]  P. Thomson,et al.  Tabular techniques for Reed—Muller logic , 1991 .

[72]  Abid E. Almaini,et al.  Electronic Logic Systems , 1992 .

[73]  Keshab K. Parhi,et al.  High-speed VLSI arithmetic processor architectures using hybrid number representation , 1992, J. VLSI Signal Process..

[74]  M. Dugdale.  VLSI implementation of residue adders based on binary adders , 1992 .

[75]  H. M. Razavi,et al.  Design of a residue arithmetic multiplier , 1992 .

[76]  Sung-Ming Yen,et al.  An efficient redundant-binary number to binary number converter , 1992 .

[77]  Vojin G. Oklobdzija,et al.  Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming , 1992, IEEE Trans. Computers.

[78]  W. Balakrishnan,et al.  Very-high-speed VLSI 2s-complement multiplier using signed binary digits , 1992 .

[79]  Marek A. Perkowski,et al.  Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[80]  Keshab K. Parhi,et al.  A fast VLSI adder architecture , 1992 .

[81]  A. J. McAuley.  Dynamic asynchronous logic for high-speed CMOS systems , 1992 .

[82]  J. M. Saul.  Logic synthesis for arithmetic circuits using the Reed-Muller representation , 1992, [1992] Proceedings The European Conference on Design Automation.

[83]  Naofumi Takagi,et al.  A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation , 1992, IEEE Trans. Computers.

[84]  Jon C. Muzio,et al.  Boolean Matrix Transforms for the Minimization of Modulo-2 Canonical Expansions , 1992, IEEE Trans. Computers.

[85]  M. Perkowski,et al.  Canonical restricted mixed-polarity exclusive-OR sums of products and the efficient algorithm for their minimisation , 1993 .

[86]  Hiroshi Makino,et al.  A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[87]  G. A. Khuwaja,et al.  Tabular simplification method for switching functions expressed in Reed-Muller algebraic form , 1993 .

[88]  Chong-Min Kyung,et al.  Design of compact static CMOS carry look-ahead adder using recursive output property , 1993 .

[89]  C. Y. Roger Chen,et al.  Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering , 1993, 30th ACM/IEEE Design Automation Conference.

[90]  A. Tran,et al.  Minimization of multiple-output exclusive-OR switching functions , 1993 .

[91]  A. Tran,et al.  Decomposition method for minimisation of Reed-Muller polynomials in mixed polarity , 1993 .

[92]  Mostafa Abd-El-Barr,et al.  On the optimization of MOS circuits , 1993 .

[93]  J. Miller,et al.  Optimization of Reed-Muller logic functions , 1993 .

[94]  A. E. A. Almaini,et al.  A simple and high speed CMOS carry chain adder architecture , 1993 .

[95]  Tsutomu Sasao.  And-Exor Expressions and their Optimization , 1993 .

[96]  J. M. Saul,et al.  Technology mapping of mixed polarity Reed-Muller representations , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[97]  J. Saul,et al.  Two-level logic circuits using EXOR sums of products , 1993 .

[98]  Tsutomu Sasao.  Logic Synthesis with Exor Gates , 1993 .

[99]  A. Tran,et al.  Generalisation of tri-state map and a composition method for minimisation of Reed-Muller polynomials in mixed polarity , 1993 .

[100]  Vitit Kantabutra.  Designing Optimum One-Level Carry-Skip Adders , 1993, IEEE Trans. Computers.

[101]  I. Koren.  Computer arithmetic algorithms , 2018 .

[102]  D. K. Bradley,et al.  Designing Optimum One-Level Carry-Skip Adders , 1993 .

[103]  D. Green.  Dual forms of Reed-Muller expansions , 1994 .

[104]  Z. Guan.  Logic realization using mixed representations based on Reed-Muller forms , 1994 .

[105]  Xiaoping Huang,et al.  A high-performance CMOS redundant binary multiplication-and-accumulation (MAC) unit , 1994 .

[106]  Dhananjay S. Phatak,et al.  Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains , 1994, IEEE Trans. Computers.

[107]  Z. Guan,et al.  A parallel CMOS 2's complement multiplier based on 5:3 counter , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[108]  S. Moh,et al.  Serial-parallel multiplier for two's complement numbers , 1995 .

[109]  Digit-Set Conversions: Generalizations and Applications , 1995 .

[110]  A. E. A. Almaini,et al.  One-bit adder design based on Reed-Muller expansions , 1995 .

[111]  D. M. Miller,et al.  Upper bound on number of products in AND-OR-XOR expansion of logic functions , 1995 .

[112]  Tsutomu Sasao,et al.  Logic Synthesis and Optimization , 1997 .

[113]  Amar Aggoun.  New parallel multiplier design , 1997, Remote Sensing.