Design of a four phase 25% duty cycle DLL with calibration

This paper presents a design of a four phase 25% duty cycle of 400MHz DLL with calibration. To avoid the disadvantages of digital calibration method, it introduced an all-analog calibration method. Instead of DAC, CP is used in calibration loop to save power consumption and area occupying. With a 4 channel time-interleaved 6 bit flash ADC, the simulated results show that SNR is 30.8dB and 43.6dB with 800MHz input with and without calibration respectively.

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