Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
暂无分享,去创建一个
[1] Carl Ebeling,et al. RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.
[2] Robert K. Brayton,et al. Improvements to Technology Mapping for LUT-Based FPGAs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Jinmei Lai,et al. A new FPGA packing algorithm based on the modeling method for logic block , 2005, 2005 6th International Conference on ASIC.
[4] Kenneth B. Kent,et al. Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.
[5] Julio A. de Oliveira Filho,et al. CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[6] Jason Luu,et al. VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling , 2009, FPGA '09.
[7] Guy Lemieux,et al. Design of interconnection networks for programmable logic , 2003 .
[8] Jason Helge Anderson,et al. Architecture-specific packing for virtex-5 FPGAs , 2008, FPGA '08.
[9] Carl Ebeling,et al. PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.
[10] Jason Luu,et al. A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs , 2010 .
[11] Majid Sarrafzadeh,et al. Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs , 2004, J. Circuits Syst. Comput..
[12] Zvonko G. Vranesic,et al. Fundamentals of Digital Logic with Verilog Design , 1999 .
[13] Jason Cong,et al. Optimal simultaneous mapping and clustering for FPGA delay optimization , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[14] Wayne Luk,et al. Floating-Point FPGA: Architecture and Modeling , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[15] S. Yang,et al. Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .
[16] Reiner W. Hartenstein,et al. Field-Programmable Logic Smart Applications, New Paradigms and Compilers , 1996, Lecture Notes in Computer Science.
[17] Vaughn Betz,et al. Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.
[18] Larry McMurchie,et al. Emerald - An Architecture-Driven Tool Compiler for FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.
[19] Steven J. E. Wilton,et al. An SRAM-programmable field-configurable memory , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.
[20] Prabhat Mishra,et al. Architecture description languages for programmable embedded systems , 2005 .
[21] Sungmin Cho,et al. Combinational and sequential mapping with priority cuts , 2007, ICCAD 2007.
[22] Daniele Giuseppe Paladino,et al. Academic Clustering and Placement Tools for Modern Field-Programmable Gate Array Architectures , 2008 .
[23] Andrew A. Kennings,et al. Improving Timing-Driven FPGA Packing with Physical Information , 2007, 2007 International Conference on Field Programmable Logic and Applications.
[24] Alan Mishchenko,et al. WireMap: FPGA technology mapping for improved routability , 2008, FPGA '08.
[25] Malgorzata Marek-Sadowska,et al. Efficient circuit clustering for area and power reduction in FPGAs , 2002, TODE.
[26] Kenneth B. Kent,et al. VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling , 2011, TRETS.
[27] Vaughn Betz,et al. Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density , 1999, FPGA '99.
[28] Jianwen Zhu,et al. Scalable Synthesis and Clustering Techniques Using Decision Diagrams , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[29] Vaughn Betz,et al. Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.
[30] Xuegong Zhou,et al. A novel packing algorithm for sparse crossbar FPGA architectures , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
[31] SinghAmit,et al. Efficient circuit clustering for area and power reduction in FPGAs , 2002 .
[32] Robert K. Brayton,et al. Combinational and sequential mapping with priority cuts , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[33] C. M. Sperberg-McQueen,et al. Extensible Markup Language (XML) , 1997, World Wide Web J..