Plug-In Timing Models for an Abstract Timing Verifier

We have developed the concept of an abstract timing verifier that accepts plug-compatible timing models in a common framework containing the scheduling algorithms and the user interface. Depending on the design phase and the particular level of design representation used, the most suitable timing model can be plugged into this framework and operated in a standard way. This paper formally introduces the abstract timing model and defines the operations that need to be carried out in such models. It discusses the models used in existing commercial timing verifiers in this context and compares them against some new and modified models. It presents some guidelines for the extension of this library of timing models.

[1]  Norman P. Jouppi,et al.  Timing Analysis for nMOS VLSI , 1983, 20th Design Automation Conference Proceedings.

[2]  T.M. McWilliams.  Verification of Timing Constraints on Large Digital Systems , 1980, 17th Design Automation Conference.

[3]  John K. Ousterhout.  A Switch-Level Timing Verifier for Digital MOS VLSI , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[5]  T. I. Kirkpatrick,et al.  PERT as an aid to logic design , 1966 .

[6]  James E. Smith,et al.  Developments in Logic Network Path Delay Analysis , 1982, DAC 1982.

[7]  A. Nadas,et al.  Probabilistic PERT , 1979 .

[8]  John K. Ousterhout.  Switch-Level Delay Models for Digital MOS VLSI , 1984, 21st Design Automation Conference Proceedings.

[9]  Robert B. Hitchcock,et al.  Timing verification and the timing analysis program , 1988, DAC 1982.

[10]  James H. Shelly,et al.  Statistical Techniques of Timing Verification , 1983, 20th Design Automation Conference Proceedings.