Architectural considerations for a self-timed decoupled processor
暂无分享,去创建一个
[1] Doug Hunt,et al. Advanced performance features of the 64-bit PA-8000 , 1995, Digest of Papers. COMPCON'95. Technologies for the Information Superhighway.
[2] Wm. A. Wulf. The WM computer architecture , 1988, CARN.
[3] Henry M. Levy,et al. Hardware and software support for efficient exception handling , 1994, ASPLOS VI.
[4] Andrew R. Pleszkun,et al. PIPE: a VLSI decoupled architecture , 1985, ISCA '85.
[5] Erik Brunvand,et al. Precise exception handling for a self-timed processor , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[6] Pius Ng,et al. A comparision of superscalar and decoupled access/execute architectures , 1993, MICRO 1993.
[7] Erik Brunvand,et al. Fred: an architecture for a self-timed decoupled computer , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[8] Harry Dwyer,et al. An out-of-order superscalar processor with speculative execution and fast, precise interrupts , 1992, MICRO 25.
[9] Andrew R. Pleszkun,et al. Implementation of the PIPE processor , 1991, Computer.
[10] M. K. Farrens,et al. Improving performance of small on-chip instruction caches , 1989, ISCA '89.
[11] Andrew R. Pleszkun,et al. WISQ: a restartable architecture using queues , 1987, ISCA '87.