Performance enhancement in active power filter (APF) by FPGA implementation

The generated electrical power in present days is not able meet its end user requirement as power demand is gradually increasing and expected to be increasing more in future days. In the power quality management the parameters/factors like harmonic currents (HC) and reactive power (RP) yields the major issues in the power distribution units causing transformer heating, line losses and machine vibration. In order to overcome these issues several control mechanisms has been presented and implemented in recent past. The mechanism procedure based on synchronous reference frame (SRF) offers better response by dividing the HC and RP. But the SRF based mechanism procedure requires better synchronization among the utility voltage and input current. To achieve this, the existing researches have used digital signal processing (DSP) and microcontroller but these systems fails to provide better performance as they face issues like limited sampling time, less accuracy and high computational complexity. Thus, to enhance the performance of active power filter (APF) we present FPGA based methodology. Also, the performance authorization of the proposed approach, we have used Xilinx 14.7 and Modelsim (6.3f) simulator and compared with the work of [14]. From the results analysis it is found that the approach has got better performance than [14].