Semi-empirical RF MOST model for CMOS 65nm technologies

This paper presents a simple but accurate semi-empirical model especially focused on 65nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio g m / I D . Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS-LNA), in 2.5GHz and 5.3GHz RF applications is picked. For the presented set of designs different g m / I D ratios are considered. Finally, the computed results are assessed by comparing with the outcomes of electrical simulations.. HighlightsTheory, extraction method and validation of accurate semi-empirical MOS model.Method focused on nanometer technologies and radio-frequency applications.The set of characteristics is extracted for 65-nm bulk CMOS RF transistors.Model extracted from dc and noise electrical simulations as functions of gm/ID.The model describes dc normalized current and all transconductances versus gm/ID.The model relates normalized intrinsic capacitances versus gm/ID.The model describes flicker and white noise parameters as function of gm/ID.A set of CS-LNAs are designed and simulated electrically to validate the model.

[1]  Antonio Cerdeira,et al.  Optimised design of an organic thin-film transistor amplifier using the gm/ID methodology , 2012, IET Circuits Devices Syst..

[2]  G. Gildenblat,et al.  PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation , 2006, IEEE Transactions on Electron Devices.

[3]  A. Dragone,et al.  Noise in Charge Amplifiers—A $g_{m}/I_{D}$ Approach , 2012, IEEE Transactions on Nuclear Science.

[4]  Chien-Nan Jimmy Liu,et al.  Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Carlos Galup-Montoro,et al.  An MOS transistor model for analog circuit design , 1998, IEEE J. Solid State Circuits.

[6]  Francisco V. Fernández,et al.  Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Fernando Silveira,et al.  CMOS op-amp power optimization in all regions of inversion using geometric programming , 2008, SBCCI '08.

[8]  Fernando Silveira,et al.  LC-VCO Design Optimization Methodology Based on the $g_m/I_D$ Ratio for Nanometer CMOS Technologies , 2011, IEEE Transactions on Microwave Theory and Techniques.

[9]  Denis Flandre,et al.  Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology , 1997 .

[10]  P. Heydari,et al.  Ultra-low power RFIC design using moderately inverted MOSFETs: an analytical/experimental study , 2006, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006.

[11]  Denis Flandre,et al.  A modified gm/ID design methodology for deeply scaled CMOS technologies , 2014 .

[12]  Fernando Silveira,et al.  MOST Moderate–Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs , 2014, IEEE Transactions on Microwave Theory and Techniques.

[13]  Dominique Savignac,et al.  Unified complete MOSFET model for analysis of digital and analog circuits , 1994, ICCAD '94.

[14]  Denis Flandre,et al.  A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA , 1996, IEEE J. Solid State Circuits.

[15]  Chien-Nan Kuo,et al.  A 0.6-V 0.33-mW 5.5-GHz Receiver Front-End Using Resonator Coupling Technique , 2011, IEEE Transactions on Microwave Theory and Techniques.

[16]  J.-P. Raskin,et al.  Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization , 2006, IEEE Transactions on Electron Devices.

[17]  Ming Gu,et al.  Synthesis of Bias-Scalable CMOS Analog Computational Circuits Using Margin Propagation , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.