A 1.8GHz wide-band stacked-cascode CMOS power amplifier for WCDMA applications in 65nm standard CMOS

A two-stage power amplifier (PA) for WCDMA operation in standard 65-nm CMOS is presented. The power amplifier delivers a saturated output power of 29.4 dBm at a power-added efficiency of 51% operating from a 3.4V supply at 1.8GHz. A two-stage interstage matching network was employed to achieve a high bandwidth of more than 300MHz where the amplifier shows a high PAE of more than 45%. With a WCDMA input signal a maximum linear output power (@ ACLR=−33 dBc) of 25.4 dBm was measured, corresponding to a linear PAE of 37.9% without digital predistortion (DPD). Using DPD, these figures could be improved to 27.9 dBm and 48%.

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