Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent @p-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.