Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

This paper introduces a new distributed active MOSFET rail clamp network that offers surprising advantages in layout area efficiency, bus resistance tolerance, design modularity and ease of reuse. SPICE simulation results using an extended vertical PNP bipolar transistor compact model and a new method for optimizing distributed rail clamp networks are presented along with chip-level test results.

[1]  H. Stubing,et al.  A compact physical large-signal model for high-speed bipolar transistors at high current densities—Part I: One-dimensional model , 1987, IEEE Transactions on Electron Devices.

[2]  Steven H. Voldman,et al.  ESD protection in a mixed-voltage interface and multirail disconnected power grid environment in 0.50- and 0.25-/spl mu/m channel length CMOS technologies , 1995 .

[3]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[4]  J.W. Miller,et al.  Engineering the cascoded NMOS output buffer for maximum V/sub t1/ , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[5]  E. Worley,et al.  Sub-micron chip ESD protection schemes which avoid avalanching junctions , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[6]  Timothy J. Maloney,et al.  Designing on-chip power supply coupling diodes for ESD protection and noise immunity☆ , 1994 .

[7]  Sung-Mo Kang,et al.  Modeling of Electrical Overstress in Integrated Circuits , 1994 .

[8]  W.R. Anderson,et al.  Cross-referenced ESD protection for power supplies [microprocessors] , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[9]  Paolo Antognetti,et al.  Semiconductor Device Modeling with Spice , 1988 .

[10]  A. Amerasekera,et al.  Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[11]  M. Schroter,et al.  A compact physical large-signal model for high-speed bipolar transistors at high current densities—Part II: Two-dimensional model and experimental results , 1987, IEEE Transactions on Electron Devices.

[12]  S. Ghandhi.  Semiconductor power devices , 1977 .

[13]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[14]  E. Worley,et al.  High current characteristics of devices in a 0.18 /spl mu/m CMOS technology , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[15]  Michael Schroter,et al.  A compact bipolar transistor model for very-high-frequency applications with special regard to narrow emitter stripes and high current densities , 1993 .

[16]  Timothy J. Maloney,et al.  Basic ESD and I/O Design , 1998 .

[17]  Amitava Chatterjee,et al.  Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow , 1992 .

[18]  S. Furkay,et al.  Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[19]  Steven H. Voldman,et al.  Shallow trench isolation double-diobe electrostatic discharge circuit and interaction with DRAM output circuitry , 1993 .

[20]  Timothy J. Maloney,et al.  Novel clamp circuits for IC power supply protection , 1995 .