Differential pixel-based low-power and high-speed implementation of DCT for on-board satellite image processing

Low-power and high-speed discrete cosine transform (DCT) implementation of the images captured by the satellites presents a hardware design problem. The cost of the DCT implementation is dominated by the complexity of the multiplication of input data (image) with the DCT matrix. The techniques for minimising the complexity of multiplication by employing a differential pixel method are presented. In the proposed method 8×8 blocks of input image matrix are considered, the difference between the adjacent pixels is calculated and those differential pixels are used in DCT transformation. Synthesis results on 0.18 µm CMOS technology show that the proposed method gives an average of 13.2% reduction in power consumption and 10.9% improvement in speed over the conventional method. The proposed method can also be combined with the common subexpression elimination method for further reduction.

[1]  Debashis Bhattacharya,et al.  Algorithms for low power and high speed fir filter realization using differential coefficients , 1997 .

[2]  Kai Hwang,et al.  Advanced computer architecture - parallelism, scalability, programmability , 1992 .

[3]  E.M.-K. Lai,et al.  Hardware efficient DCT implementation for portable multimedia terminals using subexpression sharing , 2004, 2004 IEEE Region 10 Conference TENCON 2004..

[4]  Weiping Li,et al.  DCT/IDCT processor design for high data rate image coding , 1992, IEEE Trans. Circuits Syst. Video Technol..

[5]  Chein-Wei Jen,et al.  A New Array Architecture for Prime-Length Discrete Cosine Transform , 1993, IEEE Trans. Signal Process..

[6]  Chein-Wei Jen,et al.  The efficient memory-based VLSI array designs for DFT and DCT , 1992 .

[7]  R. Hartley.  Subexpression sharing in filters using canonic signed digit multipliers , 1996 .

[8]  Jiun-In Guo,et al.  An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization , 2004, IEEE Transactions on Circuits and Systems for Video Technology.

[9]  Tughrul Arslan,et al.  Low power DCT implementation approach for VLSI DSP processors , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[10]  Nicolas Boullis,et al.  Some optimizations of hardware multiplication by constant matrices , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[11]  Miodrag Potkonjak,et al.  Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  A. Prasad Vinod,et al.  An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Dong Sam Ha,et al.  Low power design of DCT and IDCT for low bit rate video codecs , 2004, IEEE Transactions on Multimedia.

[14]  N. Ahmed,et al.  Discrete Cosine Transform , 1996 .

[15]  Ming-Chang Wu,et al.  A unified systolic array for discrete cosine and sine transforms , 1991, IEEE Trans. Signal Process..

[16]  Jiun-In Guo,et al.  A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).