VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms: 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8–10, 2018, Revised and Extended Selected Papers

A synthesizable digital LDO implemented with standardcell-based digital design flow is proposed. The difference between output and reference voltages is converted into delay difference using inverter chains as voltage-controlled delay lines, then compared in the timedomain. Since the time-domain difference is straightforwardly captured by a simple DFF-based phase detector, the proposed LDO does not need an analog voltage comparator, which requires careful manual design. All the components in the LDO can be described with Verilog codes based on their specifications, and placed-and-routed with a commercial EDA tool. This automated layout design relaxes the burden and time of implementation, and enhances process portability. The proposed LDO implemented in a 65 nm standard CMOS technology occupies 0.015 mm area. With 10.4 MHz internal clock, the tracking response of the LDO to 200 mV switching in the reference voltage is ∼4.5μs and the transient response to 5 mA change in the load current is ∼6.6μs. At 10 mA load current, the quiescent current consumed by the LDO core is as low as 35.2μA, which leads to 99.6% current efficiency.