A 372 ps 64-bit adder using fast pull-up logic in 0.18µm CMOS

This paper presents a 372 ps 64-bit adder using fast pull-up logic (FPL) in 0.18 /spl mu/m CMOS technology. Fast pull-up logic is devised and applied to decrease pull-up time which is critical in domino-static adder. The implemented adder measures the worst case delay of 372 ps. The adder has a modified tree architecture using load distribution method and has 6 logic stages.

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